International Business Machines Corporation

Daniel A Delibac

David C Thomas

Matthew D Moon

Shawn A Adderly

Zhong-Xiang He

Timothy Dooling Sullivan

Tom C Lee

William Joseph Murphy

Jonathan Daniel Chapple-Sokol

Daniel Scott Vanslette

David A DeMuynck

Craig E Schneider

Shawn R Goddard

Melissa J Roma

Kyle Babinski

Jeffrey P Gambino

Eric Jeffrey White

Anthony C Speranza

Brian M Czabaj

Disclosed is a method of manufacturing integrated circuit (IC) chips. In the method, wafers are received and the backside roughness levels of these wafers are determined. Based on the backside roughness levels, the wafers are sorted into different groups. Chips having the same design are manufactured on wafers from all of the different groups. However, during manufacturing, process(es) is/are performed differently on wafers from one or more of the different groups to minimize systematic variations in a specific parameter (e.g., wire width) in the resulting chips. Specifically, because systematic variations may occur when the exact same processes are used to form IC chips on wafers with different backside roughness levels, the method disclosed herein selectively adjusts one or more of those processes when performed on wafers from one or more of the different groups to ensure that the specific parameter is approximately equal in the resulting integrated IC chips.

Method of fine-tuning process controls during integrated circuit chip manufacturing based on substrate backside roughness

Disclosed are semiconductor structures with metal lines and methods of manufacture which reduce or eliminate extrusion formation. The method includes forming a metal wiring comprising a layered structure of metal materials with an upper constraining layer. The method further includes forming a film on the metal wiring which prevents metal extrusion during an annealing process.

Semiconductor structures with metal lines

Aspects of the present invention relate to method for reducing lateral extrusion formed in semiconductor structures and semiconductor structures formed thereof. Various embodiments include a method for reducing lateral extrusion formed in semiconductor structures. The method can include removing a portion of a first lateral extrusion in an aluminum layer of the semiconductor structure, and determining a post-removal thickness of a dielectric layer positioned adjacent the aluminum layer. The post-removal thickness may be determined subsequent to the removing of the portion of the first lateral extrusion. The method can also include determining a difference between the post-removal thickness of the dielectric layer and a pre-removal thickness of the dielectric layer.

Method for reducing lateral extrusion formed in semiconductor structures and semiconductor structures formed thereof

A vertical metallic stack, from bottom to top, of an elemental metal liner, a metal nitride liner, a Ti liner, an aluminum portion, and a metal nitride cap, is formed on an underlying metal interconnect structure. The vertical metallic stack is annealed at an elevated temperature to induce formation of a TiAlliner by reaction of the Ti liner with the material of the aluminum portion. The material of the TiAlliner is resistant to electromigration, thereby providing enhanced electromigration resistance to the vertical metallic stack comprising the elemental metal liner, the metal nitride liner, the TiAlliner, the aluminum portion, and the metal nitride cap. The effect of enhanced electromigration resistance may be more prominent in areas in which the metal nitride cap suffers from erosion during processing.

Electromigration resistant aluminum-based metal interconnect structure

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Colchester, VT, United States of America

Daniel A Delibac