International Business Machines Corporation

Samsung Electronics Co., Ltd.

Freescale Semiconductor,inc.

Globalfoundries Singapore Pte. Ltd.

Daniel A Corliss

Dario Leonardo Goldfarb

Fee Li Lie

Kamal Kumar Sikka

Dinesh Gupta

Donald Francis Canaperi

Michael A Guillorn

Shawn Peter Fetterolf

Christopher Frederick Robinson

Derren Neylon Dunn

Steven J Holmes

Rudy J Wojtecki

Ekmini Anuja De Silva

Nelson M Felix

David V Horak

Oleg Gluschenkov

Richard Stephan Wise

Veeresh Vidyadhar Deshpande

Kevin R Winstel

Ravi K Bonam

Iqbal Rashid Saraf

Sadanand Vinayak Deshpande

Kurt R Kimmel

Luciana Meli Thompson

Sivarama Krishnan

Toshiharu Furukawa

Mark Charles Hakey

Charles W Koburger, Iii

Christopher P Ausschnitt

Timothy A Brunner

Scott David Halle

Karen Elizabeth Petrillo

Christopher J Progler

Shahid Ahmad Butt

Dario Gil

Michael James Lercel

Dmitriy Shneyder

Nakgeuon Seong

Richard C Johnson

Sohan Singh Mehta

Hyung-Rae Lee

Dong Hee Yu

Chumeng Zheng

Niall Shepherd

The subject disclosure relates to 3D microelectronic chip packages with embedded coolant channels. The disclosed 3D microelectronic chip packages provide a complete and practical mechanism for introducing cooling channels within the 3D chip stack while maintaining the electrical connection through the chip stack. According to an embodiment, a microelectronic package is provided that comprises a first silicon chip comprising first coolant channels interspersed between first thru-silicon-vias (TSVs). The microelectronic chip package further comprises a silicon cap attached to a first surface of the first silicon chip, the silicon cap comprising second TSVs that connect to the first TSVs. A second silicon chip comprising second coolant channels can further be attached to the silicon cap via interconnects formed between a first surface of the second silicon chip and the silicon cap, wherein the interconnects connect to the second TSVs.

Three-dimensional microelectronic package with embedded cooling channels

An embodiment of the invention may include a method for ensuring semiconductor design integrity. The method may include analyzing a photomask design for a semiconductor circuit. The photomask may include a primary electrical design necessary for the operation of the semiconductor circuit, and white space, which has no primary electrical design. The method may include inserting a secondary electrical design into the white space of the photomask design for the semiconductor circuit. The secondary electrical design may have known electrical properties for validating the semiconductor circuit design.

Electrical mask validation

A lithographic patterning method includes forming a multi-layer patterning material film stack on a semiconductor substrate, the patterning material film stack including a resist layer formed over one or more additional layers, and forming a metal-containing top coat over the resist layer. The method further includes exposing the multi-layer patterning material film stack to patterning radiation through the metal-containing top coat to form a desired pattern in the resist layer, removing the metal-containing top coat, developing the pattern formed in the resist layer, etching at least one underlying layer in accordance with the developed pattern, and removing remaining portions of the resist layer. The metal-containing top coat can be formed, for example, by atomic layer deposition or spin-on deposition over the resist layer, or by self-segregation from the resist layer.

Patterning material film stack with metal-containing top coat for enhanced sensitivity in extreme ultraviolet (EUV) lithography

A stacked semiconductor microcooler includes a first and second semiconductor microcooler. Each microcooler includes silicon fins extending from a silicon substrate. A metal layer may be formed upon the fins. The microcoolers may be positioned such that the fins of each microcooler are aligned. One or more microcoolers may be thermally connected to a surface of a coolant conduit that is thermally connected to an electronic device heat generating device, such as an integrated circuit (IC) chip, or the like. Heat from the electronic device heat generating device may transfer to the one or more microcoolers. A flow of cooled liquid may be introduced through the conduit and heat from the one or more microcoolers may transfer to the liquid coolant.

Semiconductor microcooler

A stacked semiconductor microcooler includes a first microcooler and a second microcooler. The microcoolers may be positioned such that the fins of each microcooler are vertically aligned. The microcoolers may include an inlet passage to accept coolant and an outlet passage to expel the coolant. One or more microcoolers may be thermally connected to an electronic device heat generating device, such as an integrated circuit (IC) chip, or the like. Heat from the electronic device heat generating device may transfer to the one or more microcoolers. A flow of cooled liquid may be introduced through the passages and heat from the one or more microcoolers may transfer to the liquid coolant.

A semiconductor structure includes a semiconductor substrate and a multi-layer patterning material film stack formed on the semiconductor substrate. The patterning material film stack includes a resist layer formed over one or more additional layers. The semiconductor structure further includes a metal-containing top coat formed over the resist layer. The metal-containing top coat can be formed, for example, by atomic layer deposition or spin-on deposition over the resist layer, or by self-segregation from the resist layer.

Methods for determining unintentional exposure dose such as flare or out-of-band radiation of a lithography tool are provided. The methods generally include performing a series of open frame exposures with the lithography tool on a substrate having a photoresist therein to produce a primary array of controlled exposure dose blocks in the photoresist. Secondary exposure blocks are embedded within the primary array. The resultant open frame images are scanned with oblique light and the light scattered from the substrate surface captured. A haze map is created from a background signal of the captured scattered light data and converted to a graphical image file. Analyzing the graphical image file can be used to correlate any localized changes in the effective dose of the primary exposure array to the impact of secondary exposure blocks to characterize flare or out-of-band radiation associated with the exposure dose.

Lithographic dose characterization

An embodiment of the invention may include a semiconductor structure for ensuring semiconductor design integrity. The semiconductor structure may include an electrical circuit necessary for the operation of the semiconductor circuit and white space having no electrical circuit. The semiconductor structure may include an optical pattern used for validating the semiconductor circuit design formed in the white space of the electrical circuit. In an embodiment of the invention, the optical pattern may include one or more deposition layers. In an embodiment of the invention, the optical pattern may include covershapes. In an embodiment of the invention, the optical pattern may be physically isolated from the electrical circuit. The optical pattern may include a Moir&#xe9; pattern.

Semiconductor structure for optical validation

Systems, methods and computer program products generally include a vector by vector subtraction method per wafer. A first layer is exposed to form a pattern image on a wafer and the overlay data of alignment registration marks at multiple locations relative to alignment registration marks of a baseline reference are measured. The first layer is then reworked and exposed to form the same pattern image and the overlay data of alignment registration marks at multiple locations relative to alignment registration marks of a first layer are measured. The overlay data of the reworked first layer is subtracted from the overlay data of the first layer to provide an overlay difference at each of the multiple locations. The overlay difference is converted to a pre-correction factor of a magnitude opposite that of the overlay difference and is applied to exposure of a second layer provided on the first layer.

Baseline overlay control with residual noise reduction

A semiconductor microcooler is fabricated by forming fins in a semiconductor substrate and forming a metal layer upon the fins. A stacked microcooler may be formed by stacking a plurality of semiconductor microcoolers. The microcoolers may be positioned such that the fins of each microcooler are vertically aligned. The microcoolers may include an inlet passage to accept coolant and an outlet passage to expel the coolant. One or more microcoolers may be thermally connected to an electronic device heat generating device, such as an integrated circuit (IC) chip, or the like. Heat from the electronic device heat generating device may transfer to the one or more microcoolers. A flow of cooled liquid may be introduced through the passages and heat from the one or more microcoolers may transfer to the liquid coolant.

A semiconductor microcooler is fabricated by forming fins in a semiconductor substrate and forming a metal layer upon the fins. A stacked microcooler may be formed by stacking a plurality of semiconductor microcoolers. The microcoolers may be positioned such that the fins of each microcooler are aligned. One or more microcoolers may be thermally connected to a surface of a coolant conduit that is thermally connected to an electronic device heat generating device, such as an integrated circuit (IC) chip, or the like. Heat from the electronic device heat generating device may transfer to the one or more microcoolers. A flow of cooled liquid may be introduced through the conduit and heat from the one or more microcoolers may transfer to the liquid coolant.

Techniques that facilitate a copper microcooler structure are provided. In one example, a device includes a first copper microcooler structure and a second copper microcooler structure. The first copper microcooler structure includes a first copper plate and a first set of copper channels attached to the first copper plate. The second copper microcooler structure includes a second copper plate and a second set of copper channels attached to the second copper plate. A surface of the second copper plate associated with the second copper microcooler structure is bonded to one or more surfaces of the first set of copper channels associated with the first copper microcooler structure via a fusion bond.

Copper microcooler structure and fabrication

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Waterford, NY, United States of America

Daniel A Corliss