Sun Microsystems, Inc.

Chameleon Systems, Inc.

Intel Corporation

Dani Y Dakhil

Ramesh K Panwar

Peter Shing Fai Lam

Jin-Sheng Shyr

A data dependency checking table is used with a reconfigurable chip. A control processing chip on the reconfigurable chip can load variable size blocks of data to and from reconfigurable slices on the reconfigurable chip from an external memory. The dependency checking table is used to ensure data coherency. The dependency checking table stores an indication of size of the memory blocks transferred between the external memory and the reconfigurable logic slices. In a preferred embodiment, the size indication is a mask value in which reduces the computation involved in determining whether there is a potential data coherency conflict.

Dependency checking for reconfigurable logic

A method of efficiently performing transactions on the system bus which includes at least a request signal line, a grant signal line, a set of address signal lines, and a set of data signal lines in which upon the falling edge of the grant signal from the memory controller for a first memory transaction and prior to the completion of the servicing of the first memory transaction, a second memory transaction can be issued. Once a first address corresponding to the first memory transaction request is transmitted to the memory controller, the address lines are available for transmitting a second address corresponding to the second memory transaction request to the memory controller. The memory controller then stores the second address in a buffer whereupon the completion of servicing the first memory transaction request, the second request can be serviced without waiting for the second request arbitration process or for the address to be transmitted to the memory controller. In addition, in another aspect of the method for efficiently utilizing the system bus, register transactions between system sub-blocks and the system's central processing unit are performed using the system bus by multiplexing register data onto the address signal lines of the system bus when the address signal lines are idle, thereby further minimizing address line idle cycles.

Efficient system bus architecture for memory and register transfers

A configuration bit layout for a reconfigurable chip includes address bits stored along with configuration bits. The blocks of data are loaded onto the reconfigurable chip from an external memory and the address information is decoded to load the configuration bits onto the correct locations in the reconfigurable chip. In this way, configuration data need not be stored sequentially in the external memory. Configurations can be allocated into different slices of the reconfigurable chip as well.

Configuration bits layout

A system and method of detecting events such as DMA requests, computation operations, configuration set-up operations, occurring in a processing system which are performed by functional system blocks within the system by using logic flags stored in registers within each of the functional system blocks. The registers are coupled to the CPU on dedicated signal lines. Each time a functional block completes an operation or function it updates its corresponding logic flag. The CPU monitors the state of the flags to determine whether certain events have taken place in the system in order to sequentially coordinate functions and operations within the system without the use of interrupt signals on the system bus.

Logic flag registers for monitoring processing system events

A system and method of increasing the efficiency of a data processing system by alternately streaming portions of a large block of data from a large memory area into two memory banks within a smaller memory area using consecutive DMA transactions. Each streaming DMA transaction is entered in a DMA transaction queue and once it becomes active, transfers a block of data, the same size as one of the two memory banks, into one of the memory banks, after which it becomes inactive and is re-entered in the queue. When the streaming DMA transaction becomes active again, it switches to a different memory bank address and continues in the large data block where it stopped last time it was active. The streaming DMA transaction continues to be circulated in the queue until a total number of transaction iterations is reached, at which point the streaming DMA transaction is complete and is removed from the queue.

DMA data streaming

In a processor that executes complex instructions which are expanded into microinstructions prior to execution, non-complex instruction execution is optimized by providing a by-passable helper logic for expanding complex instructions into microinstructions. Control logic parses a bundle of instructions into sub-bundles of non-complex instructions and sub-bundles of microinstructions. The control logic detects when a complex instruction is present in a bundle of instructions and directs the complex instruction to the helper logic for expansion into two or more microinstructions. Each non-complex instruction bypasses the helper logic, thereby improving the execution performance of the non-complex instruction.

Fetching and handling a bundle of instructions comprising instructions

In a processor speculatively executing instructions which specify logical addresses, a method and apparatus for speculatively converting logical addresses to physical addresses. The processor has a register window movable within a register file, a window pointer register maintaining a value corresponding to the location of the window in the register file, a speculative window pointer register maintaining a speculative value of the window pointer register. A controller identifies an instruction expected to modify the value in the window pointer register, and in response to identifying the instruction the controller modifies the speculative value. A mapper, coupled to the speculative window pointer register, converts the instruction specified logical addresses to physical addresses based on the speculative value contained in the speculative window pointer register.

Apparatus for handling register windows in an out-of-order processor

In a processor executing instructions speculatively or out-of-order, a dependency table tracks instruction dependencies between a current instruction and a live instruction. The table contains an instruction identifier and the destination register specified by the live instruction. The table can also contain information about the age of the entry, the validity of the entry, and the process which the entry is associated. A dependency between instructions is determined by one or more comparators comparing the destination register to the source registers of the current instruction. True dependencies are distinguished from false dependencies using the age information, the validity information, and the process information.

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Campbell, CA, United States of America

Dani Y Dakhil