Integrated Device Technology, Inc.

Watasensor, Inc.

Danh Le Ngoc

John R Mick

Michael J Miller

Philip A Bourekas

Scott Revak

Kajiro Watanabe

George Fuh Hwang

Fulam Au

Embodiments of the present disclosure include an apparatus comprising an electronic device, a first magnet, and an inductive coil surrounding a magnetically susceptible core, wherein movement of the first magnet relative to the magnetically susceptible core changes a magnetic flux in the magnetically susceptible core to produce a current in the inductive coil, and in accordance therewith, provide power to the electronic device.

Magnetic power generation

Using a separate data register effectively increases the efficiency of an on-chip write buffer implemented as a FIFO structure. The separate register holds the output data during write cycles, allowing the write buffer FIFO to make the space consumed by the current write available at the start, rather than at the end of the write cycle. This effectively makes the write buffer 'four and one-half' entries deep, thereby increasing performance of the buffer without adding additional FIFO entries.

Use of a data register to effectively increase the efficiency of an

A parallel-to-serial FIFO buffer device (100) employs a FIFO buffer (110) for storing words of data; a tap-shift-register portion (112); and a data-shift-register portion (116) for converting from parallel to serial format words of data stored in the FIFO buffer (110), tap-shift-register portion (112) controls the conversion process, receives (150) a serial-input-expansion (RSIX) input signal, and develops (170) a serial-output-expansion (RSOX) output signal. The serial-input-expansion input signal (150) and the serial-output-expansion output signal (170) permit the device (100) to be connected with one, or more, similar, device(s) for word length and/or depth expansion.

Cascadable parallel to serial converter using tap shift registers and

For use in calculating discrete, fast fourier transformations, an arithmetic logic unit includes a number of multiplexers and registers, which, in combination, form a configurable pipeline, register ('A'), that functions as a four-deep pipeline register, as two, two-deep, pipeline registers, or as four separate registers, to latch and 'delay' the parameter represented by the state of signals externally developed on a 'DA' bus; the combination of a funnel shifter, a merge logic unit and a multiplexer; a unit for 'bit-reverse order' addressing; and a unit for 'rounding off' certain results.

Sixteen-bit programmable pipelined arithmetic logic unit

The combination of a seven-port random access memory (RAM) unit, a funnel shifter, a mask generator, an arithmetic logic unit (ALU), a merge logic unit, a number of multiplexers, and three bi-directional data buses are configured to form a thirty-two bit, cascadable, microprogrammable, bit-slice suitable for executing complex operations such as those which require that several operands be read from the memory unit, be rotated in the funnel shifter, be operated upon by the arithmetic logic unit, be merged in the merge logic unit, and the result be written back into the memory unit all in a single cycle.

Growing community of inventors

Saratoga, CA, United States of America

Danh Le Ngoc