Etopus Technology Inc.

Link a Media Devices Corporation

Danfeng Xu

Kai Keung Chan

Yu Kou

Paul K Lai

Tze Yin Cheung

Jenn-Gang Chern

Xiaolong Liu

Hon Man Yau

A transmitter device includes a configurable timer circuit that adjusts timing of input data for serial transmission of the input data. The configurable timer circuit may be configured depending on the configured data rate of the transmitter device. In one embodiment, the configurable timer circuit includes a plurality of configurable retimers that retime the input data where at least a portion of one of the plurality of configurable retimers is enabled based on the configured data rate.

Configurable transmitter device based on data rate

A receiver having analog-to-digital converters (ADC) is disclosed. The ADCs may be reconfigured based on the insertion loss mode of the receiver. For example, different portions of a plurality of time-interleaved successive approximation (SAR) ADC slices included in at least one sub-ADC of each time-interleaved ADC may be enabled depending on which of a plurality of insertion loss modes is selected for operation of the receiver.

ADC slicer reconfiguration for different channel insertion loss

A transmitter device having a calibrator circuit is disclosed. The calibrator circuit performs duty cycle calibration and phase calibration on a plurality of clock signals of the transmitter device. In one embodiment, the phase calibration is performed based on a comparison of the clock signals to a reference clock signal from the plurality of clock signals. In another embodiment, the calibrator circuit uses fixed patterns of data signals to perform phase calibration on the plurality of clock signals.

Clock duty cycle calibration and phase calibration for high-speed transmitter

A receiver for data recovery from a channel signal of a communications channel. The receiver includes a quantization circuit to generate a quantized code corresponding to the channel signal. A first decision circuit recovers, in a first signal processing mode, digital data for the channel signal based on the quantized representation of the channel signal. A second decision circuit recovers, in a second signal processing mode, the digital data for the channel signal based on the quantized representation of the channel signal. A controller selects between the first signal processing mode and the second signal processing mode based on a parameter indicative of a signal quality of the channel signal.

Receiver for high speed communication channel

A receiver having analog-to-digital converters (ADC) is disclosed. The ADCs may be reconfigured based on the data rate of the receiver. For example, more portions of each time-interleaved ADC may be enabled to support a higher data rate of the receiver and less portions of the ADCs may be used to support a lower data rate of the receiver.

ADC reconfiguration for different data rates

A receiver having an analog to digital converter with adjustable reference voltages that are calibrated to account for process variations. The receiver comprises an analog to digital converter. The analog to digital converter includes a reference generator to generate a set of N reference voltages. The reference generator adjusts voltage levels of the set of N reference voltages based on one or more control signals. A plurality of comparators compare an input signal to the set of N reference voltages. A calibration circuit generates the one or more control signals for adjusting the voltage levels of the N reference voltages based on outputs of the comparators.

Receiver with adjustable reference voltages

A multi-mode viterbi decoder supporting different decoding modes. The viterbi decoder comprises circuitry to output one or more data symbol values. The circuitry sets the one or more data symbol values to a first quantity of unit intervals in a first decoding mode (e.g. PAM-4). The circuitry sets the one or more data symbol values to a second quantity of unit intervals in a second decoding mode (e.g. NRZ). The second quantity of unit intervals is greater than the first quantity of unit intervals. A branch metric circuit is adapted to, in the first decoding mode, generate a set of viterbi branch metrics based on the data symbol values for the first quantity of unit intervals. The branch metric circuit is adapted to, in the second decoding mode, generate the set of viterbi branch metrics based on the data symbol values for the second quantity of unit intervals.

Growing community of inventors

Cupertino, CA, United States of America

Danfeng Xu