Xilinx, Inc.

Triscend Corporation

Danesh Tavana

Wilson Kaming Yee

Victor A Holen

Stephen M Trimberger

Bernard J New

Charles R Erickson

Sridhar Krishnamurthy

Jean-Didier Allegrucci

Bart Reynolds

Fung Fung Lee

Brian Fox

Andreas Papaliolios

Arye Ziklik

Steven Winegarden

Stanley S Yang

The configurable processor system includes a processor, an internal system bus, and a programmable logic all interconnected via the internal system bus, on a single integrated circuit.

Configurable processor system unit

A method of communicating encrypted configuration data between a programmable logic device (PLD) and a storage device is included in one part of the invention. The method includes the following steps. Transmit encrypted configuration data stored in a storage device to the PLD. Decrypt the encrypted configuration data to generate a copy of the configuration data in the PLD. Configure the PLD using the copy of the configuration data. In one embodiment, the PLD transmits a key to the storage device. In another embodiment the key is separately entered into the storage device and the PLD and never transmitted between the PLD and the storage device. In another embodiment, the key is entered only into the PLD. The key is used to encrypt the configuration data.

Encryption of configuration stream

A heterogeneous integrated circuit device comprising a field programmable gate array (FPGA) programmably connected to a mask-defined application specific logic area (ASLA) on an integrated circuit thus providing a flexible low cost alternative to a homogeneous device of one type or the other. By integrating both on a single monolithic IC, the user benefits from both low cost and flexibility. Routing of signals between gate arrays and between the gate arrays and input/output (I/O) circuits is also implemented as a combination of mask-defined and programmably-configured interconnections.

Integrated circuit with field programmable and application specific

An FPGA architecture offers logic elements with direct connection to neighboring logic elements and indirect connection through a routing matrix. A logic element and a portion of the routing matrix are formed as part of a tile, and tiles are joined to form arrays of selectable size. The routing matrix includes routing lines which connect just from one tile to the next and routing lines which extend longer distances through several tiles or through the entire chip. This combination is achieved by the formation of individual tiles, all of which are identical.

FPGA architecture with repeatable titles including routing matrices and

A carry logic circuit for a programmable logic device which uses a single function generator to create a carry propagate signal (P) and an output signal (S). The function generator includes a plurality of signal generation circuits, each of which is controlled by a first input signal (A) and a second input signal (B). One of the signal generation circuits is programmed to provide a desired carry propagate signal (P) in response to the first and second input signals (A,B). The carry propagate signal (P) is transmitted for use outside of the function generator to perform a carry propagation function for the carry logic circuit. The remaining signal generation circuits are programmed to generate one or more intermediate output signals in response to the first and second input signals (A,B). These intermediate output signals, in combination with carry propagate signal (P), are representative of the desired output signal (S). The function generator also includes a signal selection circuit which is coupled to the signal generation circuits. The signal selection circuit passes a signal which is selected from the group consisting of the carry propagate signal (P) and the intermediate output signals, thereby providing the output signal (S).

Method and circuit for using a function generator of a programmable

FPGA architecture with repeatable tiles including routing matrices and

A data bus on an integrated circuit includes a series of selectors arranged in a ring, each selector having an output terminal, an enable terminal, a ring input terminal, and a data input terminal. The ring input terminal receives data from another selector in the ring. The data input terminal receives data from a data source. The output terminal supplies data to the ring input terminal of a next selector in the ring. The enable terminal receives enable signals from a data source. A selector either propagates the signal on its ring input terminal or a data signal on its data input terminal to the next selector.

Read and writable data bus particularly for programmable logic devices

In a programmable integrated circuit device, a pad interface structure is provided in which the number of pads connected to the interface structure is selectively changed without redesigning the interface structure or redesigning the chip interior.

Growing community of inventors

Mountain View, CA, United States of America

Danesh Tavana