Nvidia Corporation

Nvida Corporation

Dane Mrazek

David Brian Glasco

James C Bowman

Sameer M Gauria

Yin Fung Tang

Emmett Michael Kilgariff

Yongxiang Liu

Mark Douglas Hummel

Gregory Michael Thorson

John H Edmondson

Samuel Hammond Duncan

Sean Jeffrey Treichler

Patrick Rene Marchand

Glenn A Dearth

Larry Robert Dennison

Colyn Scott Case

Nan Jiang

James E Margeson, Iii

Ravi Kiran Manyam

Karan Gupta

Eric Anderson

Yin Fung (David) Tang

A method is provided for operating a network switch comprising a plurality of input ports and a plurality of output ports. The method comprises receiving a first data packet received via a first input port and a second data packet received via a second input port to be delivered to an egress endpoint connected to a first output port, configuring a plurality of crossbar switch units arranged in a tiled architecture to pass the first data packet to the first output port via a primary path and pass the second data packet to the first output port via a secondary path, and transmitting the first data packet and the second data packet to the egress endpoint. The first data packet and the second data packet pass through the plurality of crossbar switch units simultaneously.

Crossbar multipathing for multicast performance in tiled switches

One embodiment of the invention sets forth a control crossbar unit that is designed to transmit control information from control information generators to destination components within the computer system. The control information may belong to various traffic paradigms, such as short-latency data traffic, narrow-width data traffic or broadcast data traffic. The physical connections within the control crossbar unit are categorized based on the different types of control information being transmitted through the control crossbar unit. The physical connections belong to the following categories: one-to-one (OTO) connections, one-to-many (OTM) connections, valid-to-one (VTO) connections, valid-to-many (VTM) connections wire-to-one (WTO) connections and wire-to-many (WTM) connections.

Mitigating main crossbar load using dedicated connections for certain traffic types

One embodiment of the present invention sets forth a crossbar unit that is coupled to a plurality of client subsystems. The crossbar unit is configured to transmit data packets between the client subsystems and includes a high-bandwidth channel and a narrow-bandwidth channel. The high-bandwidth channel is used for transmitting large data packets, while the narrow-bandwidth is used for transmitting smaller data packets. The transmission of data packets may be prioritized based on the source and destination clients as well as the type of data being transmitted. Further, the crossbar unit includes a buffer mechanism for buffering data packets received from source clients until those data packets can be received by the destination clients.

Consolidated crossbar that supports a multitude of traffic types

One embodiment of the present invention sets forth a destination credit management unit (CMU) that is coupled to source clients and a destination client and manages the transmission of credits associated with the destination client to the source clients. The destination CMU receives credits from the destination client as memory spaces within the destination client free up and transmits the credits to source clients as credits are consumed by the source clients. When a data packet is received from a source client, the destination CMU returns a credit to the source client if a credit is available. If a credit is not available, then the destination CMU stalls the source client until a credit becomes available. Credits are transmitted to stalled source clients in the order in which the source clients were stalled.

Just in time distributed transaction crediting

The invention sets forth a crossbar unit that includes multiple virtual channels, each virtual channel being a logical flow of data within the crossbar unit. Arbitration logic coupled to source client subsystems is configured to select a virtual channel for transmitting a data request or a data packet to a destination client subsystem based on the type of the source client subsystem and/or the type of data request. Higher priority traffic is transmitted over virtual channels that are configured to transmit data without causing deadlocks and/or stalls. Lower priority traffic is transmitted over virtual channels that can be stalled.

Virtual channels for effective packet transfer

A vertex cache within a graphics processor is configured to operate as a conventional round-robin streaming cache when per-vertex state changes are not used and is configured to operate as a random access storage buffer when per-vertex state changes are used. Batches of vertices that define primitives and state changes are output to parallel processing units for processing according to vertex shader program. In addition to allowing per-vertex state changes, the vertex cache is configured to store vertices for primitive topologies that use anchor points, such as triangle strips, line loops, and polygons.

Vertex cache map mode for per-vertex state changes

Disclosed are an apparatus, a system, a method, a graphics processing unit ('GPU'), a computer device, and a computer medium to implement a pool of independent enhanced tags to, among other things, decouple a dependency between tags and cachelines. In one embodiment, an enhanced tag-based cache structure includes a tag repository configured to maintain a pool of enhanced tags. Each enhanced tag can have a match portion configured to form an association between the enhanced tag and an incoming address. Also, an enhanced tag can have a data locator portion configured to locate a cacheline in the cache in response to the formation of the association. The data locator portion enables the enhanced tag to locate multiple cachelines. Advantageously, the enhanced tag-based cache structure can be formed to adjust the degree of reusability of the enhanced tags independent from the degree of latency tolerance for the cacheline repository.

Enhanced tag-based structures, systems and methods for implementing a pool of independent tags in cache memories

A graphics system includes a transposer. A read scheduler utilizes a minimum cost analysis to schedule a read transfer order for the transposer to minimize the total number of passes required to process a set of input vectors.

Graphics system transposer read scheduler

Disclosed are an apparatus, a method, a programmable graphics processing unit ('GPU'), a computer device, and a computer medium to facilitate, among other things, the generation of parallel data streams to effect parallel processing in at least a portion of a graphics pipeline of a GPU. In one embodiment, an input of the apparatus receives graphics elements in a data stream of graphics elements. The graphics pipeline can use the graphics elements to form computer-generated images. The apparatus also can include a transposer configured to produce parallel attribute streams. Each of the parallel attribute streams includes a type of attribute common to the graphics elements. In one embodiment, the transposer can be configured to convert at least a portion of the graphics pipeline from a single data stream to multiple data streams (e.g., executable by multiple threads of execution) while reducing the memory size requirements to implement such a conversion.

Transposition structures and methods to accommodate parallel processing in a graphics processing unit ('GPU')

A graphics system has parallel processing units that do not share vertex information. The graphics system constructs independent batches of work for the parallel processing units in which each batch of work has a list of vertices for a set of primitives.

Primitive oriented assembly for parallel vertex/geometry processing

A system, method and computer program product are provided for texture sampling in a graphics pipeline. Initially, texture information is retrieved using texture coordinates. Thereafter, the texture information is utilized to generate results. Next, the texture information and the results are utilized to generate further results. The foregoing operation may optionally be repeated, and the results outputted.

System, method and computer program product for texture address operations based on computations involving other textures

A graphics processing system is provided. The graphics processing system includes a front end module for receiving pixel data. A setup unit is coupled to the front end module and generates parameter coefficients. A raster unit is coupled to the setup unit and generates stepping information. A virtual texturing array engine textures and colors the pixel data based on the parameter coefficients and stepping information. Also provided is a pixel engine adapted for processing the textured and colored pixel data received from the virtual texturing array engine.

Growing community of inventors

Redwood City, CA, United States of America

Dane Mrazek