Motorola Corporation

Dandas K Tang

Jhy-Jer Shieh

Timothy W Sutton

The present invention provides an output buffer on a monolithic integrated circuit with programmability, such that one of sixteen output configurations is selected for providing the proper signaling interface to peripheral devices. An input signal (SELECT) in selector circuit (12) provides the transfer of one of two sets of input data signals into function control circuit (14). With the input signal (EN) applied, control signals in the function control circuit (14) set the configuration mode for the output buffer circuit (16). The data input signal INPUT DATA, in accordance with the programmed configuration mode for the output buffer circuit (16), transitions the output signal, DBOUT. The output buffer circuit (16) is programmable for providing an open-drain output, a tri-stated output, a high current output, a low current output, a PCI output, and an output selected from two operating voltages for signal level translation functions.

Programmable output buffer and method for programming

A programmable array (10) includes an array (11) of transistor cells, output cells (26, 28, 32, 34), and two internal power busses (17, 18) which are coupled to the array (11) of transistor cells. The programmable array also includes eight output power busses (35, 36, 37, 38, 41, 42, 43, 44) coupled to the output cells (26, 28, 32, 34). The two internal power busses (17, 18) are coupled to two corresponding output power busses (35, 36) via two coupling switches (55, 56). Further, the output power busses (35, 36, 37, 41, 42, 43, 44) are coupled to each other via eight switches (45, 46, 47, 48, 51, 52, 53, 54). Different power bus routings of the programmable array (10) are realized by controlling the two coupling switches (55, 56) and the eight switches (45, 46, 47, 48, 51, 52, 53, 54).

Programmable array and method for routing power busses therein

A method and a circuit for automatically adjusting a switching threshold of an input buffer circuit (100) to conform to an input signal V.sub.IN which can be from either a TTL or a CMOS logic family. A latch circuit (120) is initialized to set the switching threshold to that of one of the logic families. A level shifting circuit (130) has a switchable load which varies the switching threshold under the control of the latch circuit (120). The amplitude of the input signal V.sub.IN is detected in a threshold detector circuit (110). If the input signal V.sub.IN is a signal from the CMOS logic family, the latch circuit (120) changes state, switching the switchable load of the level shifting circuit (130) to adjust the switching threshold of the input buffer circuit (100).

Input buffer circuit and method

A buffer circuit for programming an I/O pin of a programmable logic device to function either as a normal I/O site, a power pin, or a ground pin has been provided. The I/O pin may be programmed by a user by simply placing first and second control signals in appropriate logic states. The buffer circuit also includes a tri-state circuit for providing tri-state outputs when functioning as a normal I/O site.

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Chandler, AZ, United States of America

Dandas K Tang