Broadcom Corporation

Agere Systems Inc.

Avago Technologies General IP (singapore) Pte. Ltd.

Intel Corporation

Avago Technologies International Sales Pte. Limited

Dandan Li

Arya Behzad

Long Bu

Stephen C Au

Hung-Ming Chien

Ali Afsahi

Qiang Li

Razieh Roufoogaran

Hooman Darabi

David Garrett

Tirdad Sowlati

Rohit Gaikwad

Peter Kiss

Christopher Hull

Andrew Robert Adams

Vikram Magoon

Russell John Fagg

Jacob Jude Rael

Keith Andrews Carter

Stephen Chi-Wang Au

Jesus Arias

Choong Yul Cha

Weifeng Feng

Ali Karimi-Sanjaani

Kyujin Oh

Prasad Sitaram

Jianping Peng

A synchronous switching regulator circuit for supply regulation of a switching circuit includes a pass transistor to couple the switching circuit to a supply voltage. The synchronous switching regulator circuit further includes a switch that is operable to synchronously turn off a flow of a supply current through the pass transistor. The switching circuit can be controlled by a switching signal, and the switch can operate in synchronization with the switching circuit.

Synchronous switching regulator circuit

A wireless communication device includes a first circuit including a baseband circuit and a radio circuit, and at least one frontend module (FEM) remote from the first circuit and placed in close proximity to and coupled to at least one radio-frequency (RF) antenna. The FEM is coupled to the first circuit via interface circuitry. An FEM comprises a frontend (FE) circuit including one or more low-noise amplifiers (LNAs), one or more power amplifiers (PAs), and at least one of a multi-pole switch and a multiplexer. The multi-pole switch and the multiplexer being implemented on a first side of the FEM coupled to the interface circuitry. The interface circuitry includes at least some of filters, splitters, multi-pole switches, and multiplexers to reduce a count of interconnect routes to the at least one FEM.

Wireless transceiver with remote frontend

A circuit for phase locked loop (PLL) multiple spur cancellation includes multiple spur cancellation circuits and a number of multiplexers that are coupled to respective input ports of the spur cancellation circuits. The circuit further includes a number of demultiplexers that are coupled to respective output ports of the spur cancellation circuits. Each spur cancellation circuit can cancel a spur associated with a spur source, and input nodes of the multiplexers and output nodes of the demultiplexers are coupled to different connection points of a PLL circuit.

Simultaneous cancellation of multiple spurs from different sources

In one embodiment, a method comprising during a first calibration instance, converting at a first transconductance stage a first output voltage from a power amplifier of a transceiver to a first set of current signals; and during a second calibration instance not overlapping the first calibration instance, converting at a second transconductance stage a second output voltage from the power amplifier to a second set of current signals.

Calibration for power amplifier predistortion

To improve upon efficiency of a transmitter's power amplifier during low power operation, a switching system is used to selectively switch between different (e.g., normal and reduced) power supplies. Suitable hardware/software in the form of circuitry, logic gates, and/or code functions to process, amplify, and transmit an input RF signal and selectively switch IN/OUT a plurality of supply voltages using control logic.

Power amplifier with supply switching

Certain aspects of a method and system for mitigating effects of pulling in multiple phase locked loops in multi-standard systems may include selecting an input frequency range of operation at a voltage controlled oscillator based on a particular wireless band of operation in a system that handles a first wireless communication protocol and a second wireless communication protocol. An image rejection mixer may be enabled to generate an output signal for the particular wireless band of operation based on mixing a plurality of received signals within a selected frequency range. An in-phase (I) component and a quadrature (Q) component of the generated output signal may be generated by utilizing a RC-CR quadrature network.

Method and system for mitigating the effects of pulling in multiple phase locked loops in multi-standard systems

A low noise amplifier includes a programmable input stage, having a first gain that is programmable based on a first control signal. A programmable cascode stage, has a second gain that is programmable based on a second control signal. A programmable resistor stage controls the quality of a resonant tank circuit, based on a third control signal.

Programmable low noise amplifier and methods for use therewith

Aspects of a method and system for precise current matching in deep sub-micron technology may include adjusting a current mirror to compensate for MOSFET gate leakage currents by using feedback circuits. The feedback circuits may be implemented from active components to create active feedback circuits. If the reference current to be mirrored is noisy, a smoothing effect may be achieved by introducing a low-pass filter coupled to the current mirror design. The active feedback may comprise amplifiers, which may comprise one or more amplifier stages. The amplifier may amplify either a bias voltage error or a bias current error. Furthermore, a transimpedance amplifier may be utilized in the feedback loop. The output bias current of the current mirror may be stabilized dynamically during adjusting. Multiple current sources may be utilized in the current mirrors.

Method and system for precise current matching in deep sub-micron technology

Aspects of a method and system for use of true single phase clock (TSPC) logic for a high-speed multi-modulus divider in a phase locked loop (PLL) are provided. A fractional-N PLL synthesizer may comprise a divider that generates a divider signal from a VCO output reference signal. The divider may comprise at least one divider stage that utilizes true single phase clock (TSCP) logic D flip-flops. The first divider stage may operate at substantially the same frequency as that of the VCO signal. The divider may also re-synchronize the VCO signal and the divider signal by using at least two re-synchronization stages that utilize a TSCP logic D flip-flop and a stage for adjusting duty-duty cycle of the divider signal. The TSCP logic D flip-flops circuitry may be integrated with a two-input NAND gate or a three-input NAND gate to speed up the operation of the divider.

Method and system for use of TSPC logic for high-speed multi-modulus divider in PLL

A method and apparatus in an integrated circuit radio transceiver are operable to apply a modified control signal to drive logic that includes a plurality of first devices having a first threshold voltage and a first gate oxide thickness that are both greater than a second threshold voltage and a second gate oxide thickness for a greater second plurality of devices within the integrated circuit radio transceiver. The transceiver therefore generates a first control signal having a first magnitude operable to drive logic that includes a plurality of devices having a second threshold voltage and applies the first control signal to a level shifter to produce the modified control signal.

Method and system for implementing a PLL using high-voltage switches and regulators

Aspects of a method and system for implementing a low power, high performance fractional-N PLL synthesizer are provided. The synthesizer comprises a reference generator/buffer, a charge pump, a divider, a VCO, a loop filter, and a phase-frequency detector (PFD). The reference generator/buffer may increase the frequency of the input reference signal to the PFD. The PFD may generate a single signal for controlling the charge pump utilizing the increased frequency input reference signal and a divider signal generated by the divider whose input frequency may be substantially the same as that of a VCO output signal. The single signal charges a charge up portion of the charge pump and a charge down portion is charged by a leakage current. The VCO signal may be generated based on a filtered output of the charge pump generated by the loop filter. The divider may utilize true single phase clock (TSPC) logic.

Method and system for implementing a low power, high performance fractional-N PLL

Aspects of a method and system for a fast phase-locked loop (PLL) close-loop settling after an open-loop voltage controlled oscillator (VCO) calibration are provided. A fractional-N PLL synthesizer may comprise a VCO, a phase-frequency detector (PFD), a D flip-flop, a divider, a charge pump, and a loop filter. The synthesizer may disable the PFD based on a control signal indicating the start of VCO open-loop calibration. After open-loop calibration, the synthesizer may subsequently enable a PLL closed-loop settling and may enable the PFD to control the charge pump when the input reference signal phase lags a phase of a divider signal generated by the divider. The D flip-flop may enable and disable the PFD. During open-loop calibration, the loop filter may be discharged via a leakage current in the charge pump. During closed-loop settling, the loop filter may be charged by the charge pump via control of the PFD.

Method and system for fast PLL close-loop settling after open-loop VCO calibration

A novel circuit for obtaining the bandwidth of a phase-locked loop circuit is disclosed. The circuit adjusts a phase of a signal (reference or generated), causing the phase-locked loop circuit to adjust the frequency of its voltage-controlled oscillator as it recovers a phase lock. The circuit times the duration of the recovery stage, from which the loop bandwidth may be obtained. Adjustments to the programmable portions of the phase-locked loop may then be made in accordance with design specifications.

Phase-locked loop bandwidth calibration

A method and circuit for selecting the band of a multi-band voltage controlled oscillator in a phase locked loop is described. In one implementation, the circuit comprises a voltage controlled oscillator, a selection circuit for selecting a band for the voltage controlled oscillator from a plurality of predetermined bands, a decision circuit for determining if the selection circuit should select a new band from the plurality of predetermined bands, and a charging circuit for adjusting the input voltage into the voltage controlled oscillator.

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San Diego, CA, United States of America

Dandan Li