Beijing Vcore Technology Co., Ltd.

Dandan Huan

Zusong Li

Jiye Zhao

A method for selecting an entry of a queue in an out-of-order processor includes: acquiring a tag value of each entry in the queue; generating a mask bit vector of the queue based on the tag value of each entry; generating an executable bit vector of the queue based on whether a corresponding entry in the queue satisfies an executable condition; generating a selection bit vector of the queue based on the mask bit vector and the executable bit vector; and determining an entry corresponding to a target bit in the selection bit vector as an executable entry, in which the target bit is a first bit in the selection bit vector, and a value of the first bit is equal to a first preset value.

Method and device for selecting entry of queue in out-of-order processor

A method for solving a Cache address alias and an apparatus for solving a Cache address alias are provided. The method includes determining a corresponding first virtual address based on a received access instruction; querying an address maintenance list to determine a target item corresponding to the first virtual address when an access based on the first virtual address is not hit, information recorded in the target item including a target Tag, a target address alias bit, and a target Cache; determining a second virtual address based on the first virtual address and the target item, and setting information in the second virtual address to be invalid, in which the second virtual address and the first virtual address are mapped to the same physical address; and acquiring information corresponding to the access instruction and writing it back to the first virtual address.

Method and apparatus for solving cache address alias

A SEDRAM-based stacked Cache system is integrated in multiple layers of wafers bonded together and includes a Cache, a Cache controller and a SEDRAM controller; the multiple layers of wafers includes a SEDRAM wafer structure and a processor wafer structure; a SEDRAM unit is integrated in each layer of SEDRAM wafer in the SEDRAM wafer structure and configured as a storage space of the Cache; a CPU, the Cache controller, the SEDRAM controller and a memory controller are integrated in the processor wafer structure.

SEDRAM-based stacked cache system and device and controlling method therefor

The disclosure provides a method and an apparatus for scheduling an out-of-order execution queue in an out-of-order processor. The method includes: constructing a sequence maintenance queue with a same number of items as the out-of-order execution queue, and allocating an empty item for instructions and data entering the out-of-order execution queue, in which the sequence maintenance queue comprises at least one identity (id) field; numbering each item of the out-of-order execution queue sequentially, and recording an id number of each item of the out-of-order execution queue in the id field of the sequence maintenance queue; enabling the instructions to enter an item of the out-of-order execution queue corresponding to an id number pointed by a tail of the sequence maintenance queue; and selecting instructions in ready items for execution from the out-of-order execution queue according to id number information indicated by the sequence maintenance queue.

Method and apparatus for scheduling out-of-order execution queue in out-of-order processor

The disclosure provides a method for scheduling an out-of-order queue The method includes: adding a highest bit before each address in a reorder buffer (ROB) or in a branch reorder buffer (B-ROB), in which the addresses are entered by instructions in the out-of-order queue; adding a highest bit for a read pointer (roqhead) of the ROB or B-ROB; performing an exclusive-OR (XOR) operation on the highest bit for the roqhead and the highest bit for each of the addresses entered by two instructions to be compared, and determining addresses after the XOR operation as age information of the two instructions; and comparing the age information to determine the oldest instruction in the queue for execution in response to scheduling the out-of-order queue.

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Beijing, China

Dandan Huan