Motorola Corporation

Dana Mark Rigg

Dhiraj Kumar Gossain

Alberto J Reyes

Sleiman N Chamoun

Supamas Sirichotiyakul

Venu Vasudevan

Dinesh D Gaitonde

Hongyu Xie

Tron Kyle Womack

Mark Chase

Don Michael Gibson

James H Tolar, Ii

An object oriented test provides a hierarchy of classes under test, each of the classes under test having a predefined inheritance structure. The test provides a test class for each corresponding class under test. Each class under test has a test member function, a set state member function, a verify state member function, and a test vector which includes an initial complete state, an expected complete state, a set of function inputs for a member function being tested, and a set of expected results. The test sets an initial complete state of the test class by implicitly calling the set state member functions through the inheritance structure of the test classes. Next a member function of a desired class under test is executed. The final complete state of the class under test as well as the outputs and returned values of all member functions which were executed are compared with the set of expected results.

Method for state-based oriented testing

A method (100) and apparatus (600) estimates power of an architectural design. Power functions are generated (step 102) for standard components (20) by synthesizing to a power-measurable implementation (step 202). A behavioral description is simulated (step 106) to produce switching activity and then parsed (step 108) to compute power from power functions of instantiated standard components (steps 109, 114, 118) from switching activity (step 116). Behavioral operations are parsed (step 108) into short and long blocks based on the number of operations. Short blocks are precompiled (step 110) to produce an RTL implementation including standard components. Power is estimated from switching activity at ports and inferred nodes (step 420). Long blocks are synthesized to produce power-measurable implementations (step 112). Power is estimated with a power function from weighted switching activity at each input (steps 508, 512-514).

Architectural power estimation method and apparatus

A cell library (21) is optimized for specific operating characteristics. A stimulus file (23) is divided into a number of simulation run files. The simulation run files (27) are distributed to more than one computer work station so that the simulation of the cell occurs in parallel. The netlist (24) of each cell is parameterized to allow the cell to be changed and resimulated to better meet the specific operating characteristics. A cost function (32) is provided which uses the results of a transistor level simulation to calculate the quality of the cell design relative to the specific operating characteristics. Simulated annealing (34) is used to generate new simulation parameter values from a cost generated from the cost function (32). The cell is resimulated a number of times to optimize for the specific operating characteristics and the best design is retained for a new cell library (39). The process is repeated for each cell of the cell library (21).

Method for generating an optimized integrated circuit cell library

A hierarchical design transaction method which provides a shared project workspace and an individual user workspace. A desired portion of a hierarchical design is checked out from the shared project workspace and is edited in the individual user workspace. A new version of the desired portion of the hierarchical design is checked into the shared project workspace. Concurrently, another individual user workspace is provided, and another desired portion of the hierarchical design is checked out, edited and checked in. These steps are repeated for each of a plurality of desired portions of the hierarchical design, to continuously guarantee consistency between the shared project workspace and each individual user workspace.

Method for managing a hierarchical design transaction

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Chandler, AZ, United States of America

Dana Mark Rigg