Sandisk Technologies Inc.

Silicon Storage Technology, Inc.

Sandisk Corporation

Western Digital Technologies, Inc.

Other

Dana Lee

Bomy A Chen

Henry Chin

Jeffrey W Lutze

Changyuan Chen

Deepanshu Dutta

Gerrit Jan Hemink

Ya-Fen Lin

Yingda Dong

Feng Gao

Zhenming Zhou

Jianmin Huang

Eran Sharon

Yuniarto Widjaja

Idan Alrod

Abhijeet Manohar

Anubhav Khandelwal

John W Cooksey

Hieu Van Tran

Jun Wan

Jack Frayer

Guirong Liang

Daniel Edward Tuers

Shih-Chung Lee

Deepak Raghu

Emilio Yero

Yan Li

Vinod Robert Purayath

Chris Avila

Gautam Ashok Dusija

Takashi Whitney Orimoto

Nima Mokhlesi

Steven Theodore Sprouse

Grishma Shah

Xiying Costa

Bo Lei

Stella Achtenberg

Farookh Moogat

Bing Yeh

Sohrab Kianian

David Rozman

Alon Eyal

Jian Feng Chen

Nian Niles Yang

James K Kai

George Matamis

Jayavel Pachamuthu

Jiahui Yuan

Huai-Yuan Tseng

Henry Chien

Ken Oowada

Felix Ying-Kit Tsui

Amitay Levi

Seungjune Jeon

Hock C So

Sarath Chandran Puthenthermadam

Cynthia Hsu

Chris Nga Yee Avila

Philip David Reusswig

Pitamber Shukla

Kai Man Yue

Yaw Wen Hu

Ashish Ghai

Atsushi Suyama

Yichao Huang

Arash Hazeghi

Chung H Lam

Deepak Chandra Sekar

Masaaki Higashitani

Raghuveer S Makala

Jed Hickory Rankin

Johann Alsmeier

Vishal Sarin

Christopher John Petti

Yanli Zhang

Harish Reddy Singidi

Jeffrey Bowman Johnson

Hung Quoc Nguyen

Yao-Sheng Lee

Manuel Antonio d'Abreu

Senaka Kanakamedala

Ting Luo

Aaron Lee

Geeng-Chuan Chern

Stephen L Skala

Jonathan Huynh

Mrinal Kochar

Jeng-Wei Yang

Chun Sum Yeung

Ramy Nashed Bassely Said

Dale Warner Martin

Daxin Mao

Young Pil Kim

Chun-Ming Chen

Pao-Ling Koh

Jonathan Hsu

Parth Amin

Akira Matsudaira

Sateesh Desireddi

Alexandra Bauche

A non-volatile memory system performs an erase process followed by a program process to program blocks of memory cells. The erase process comprises erasing followed by erase verification. The system recovers data and records a strike for blocks that fail a read process. In response to a particular block having a strike, the system performs an odd/even compare process during the erase process for the particular blocks having the strike such that the odd/even compare process comprises determining whether a number of memory cells connected to even word lines that have a different erase verify result than memory cells connected to odd word lines is greater than a defect test threshold. The system retires blocks from further use for storing host data that fail the odd/even compare process even if the block passes erase verification.

Non-volatile memory with efficient testing

When erasing multiple sub-blocks of a block, erase verify is performed for memory cells connected to even word lines to generate even results and for memory cells connected to odd word lines to generate odd results. The even results and the odd results are used to determine that the erase verify process successfully completed. For each NAND string of a first sub-block, a last even result for the NAND string is compared to a last odd result for the NAND string. Despite the determination that the first sub-block successfully completed erase verify, the erasing failed for the first sub-block because the number of NAND strings that have the last even result different than the last odd result is greater than a limit. The system determines that one or more additional sub-blocks also failed erasing based on and in response to determining that the first sub-block failed erasing.

Non-volatile memory with efficient testing during erase

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures extending through the alternating stack. Each of the memory stack structures includes a vertical semiconductor channel, a tunneling dielectric layer, and a vertical stack of memory elements located at levels of the electrically conductive layers between a respective vertically neighboring pair of the insulating layers. Each of the memory elements includes a first memory material portion, and a second memory material portion that is vertically spaced from and is electrically isolated from the first memory material portion by at least one blocking dielectric material portion.

Three-dimensional memory device including multi-bit charge storage elements and methods for forming the same

A data storage device includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller is operable to measure a first threshold voltage (VT) of a memory cell under a first parameter at a read temperature and measure a second VT of the memory cell under a second parameter at the read temperature in which the first parameter is different from the second parameter. A VT correction term for the memory cell is determined based upon the first VT measurement and the second VT measurement. A read VT of the memory cell is adjusted by using the VT correction term.

Temperature variation compensation

A method for data recovery in a memory array of a non-volatile memory system, wherein the method comprises detecting an electrical short between a word line (WL) of a memory cell transistor and a local source line (LI) of a memory structure of the array, increasing an initial voltage bias at the local source line to a second voltage bias that exceeds a threshold voltage of the shorted memory cell transistor and a voltage level of a bit line of the memory structure, thereby causing a sensing current to flow in a direction from the local source line to the bit line, and sensing at a sense amplifier of the memory structure the sensing current.

Reverse sensing for data recovery in non-volatile memory structures

A device includes a memory device and a controller. The memory device includes read/write circuitry and a plurality of memory dies. The controller is coupled to the memory device. The controller is configured to, responsive to determining that at least one storage element of a first die of the plurality of memory dies has a characteristic indicative of an aging condition, increase the temperature of the first die by performing memory operations on the first die until detecting a condition related to the temperature.

Memory die temperature adjustment based on aging condition

A data storage device includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller is operable to measure a first threshold voltage (Vt) of a memory cell under a first parameter at a read temperature and measure a second Vt of the memory cell under a second parameter at the read temperature in which the first parameter is different from the second parameter. A Vt correction term for the memory cell is determined based upon the first Vt measurement and the second Vt measurement. A read Vt of the memory cell is adjusted by using the Vt correction term.

Apparatuses, systems, methods, and computer program products are disclosed for dynamic read table generation. One apparatus includes a set of non-volatile storage cells. A controller for a set of non-volatile storage cells is configured to, in response to unsuccessfully reading a storage cell of the set of non-volatile storage cells using a parameter, read the storage cell using one or more shifted values. A controller for a set of non-volatile storage cells is configured to, in response to successfully reading a storage cell using one or more shifted values, add the one or more shifted values to a storage device.

Dynamic read table generation

A device includes a memory and a controller coupled to the memory. The controller is configured to determine a temperature-based value of a search parameter in response to detecting that an error rate of a codeword read from the memory exceeds a threshold error rate. The controller is further configured to iteratively modify one or more memory access parameters associated with reducing temperature-dependent threshold voltage variation and to re-read the codeword using the modified one or more memory access parameters.

A device includes a memory device and a controller. The controller is coupled to the memory device. The controller is configured to, in response to receiving a request to perform a memory access at the memory device, determine that the memory device has a characteristic indicative of a temperature crossing. The controller is also configured to, in response to determining that the memory device has the characteristic indicative of the temperature crossing, determine that the memory device satisfies an availability criterion. The controller is further configured to, in response to determining that the memory device satisfies the availability criterion, increase a temperature of the memory device by performing memory operations on the memory device until detecting a condition related to the temperature.

Memory die temperature adjustment based on a power condition

A memory stack structure includes a cavity including a back gate electrode, a back gate dielectric, a semiconductor channel, and at least one charge storage element. In one embodiment, a line trench can be filled with a memory film layer, and a plurality of semiconductor channels can straddle the line trench. The back gate electrode can extend along the lengthwise direction of the line trench. In another embodiment, an isolated memory opening overlying a patterned conductive layer can be filled with a memory film, and the back gate electrode can be formed within a semiconductor channel and on the patterned conductive layer. A dielectric cap portion electrically isolates the back gate electrode from a drain region. The back gate electrode can be employed to bias the semiconductor channel, and to enable sensing of multinary bits corresponding to different amounts of electrical charges stored in a memory cell.

Three-dimensional memory structure having a back gate electrode

A device includes a memory device and a controller. The controller is coupled to the memory device. The controller is configured to, in response to receiving a request to perform a memory access at the memory device, determine that the memory device has a characteristic indicative of a temperature crossing. The controller is also configured to, in response to the determination, increase a temperature of the memory device by performing memory operations on the memory device until detecting a condition related to the temperature.

Techniques are described for determining whether a non-volatile memory device is defective due to a word line that programs too fast, leading to an uncorrectable amount of data errors when programing data to the word line. In one set of examples, a set of memory cells are programmed by a series of voltage pulses applied along a word line without locking out the set of memory cells. A verify operation is then performed to see if the number of memory cells programmed above the verify level is too large and, if so, an error status is returned. In other examples, a lower limit on the number of voltage pulses needed to complete programming is introduced, and if the programming completes in less than this number of voltage pulses, an error status returned. A lower limit on the number of voltage pulses can be on a state by state basis or for all data states to complete.

Determination of fast to program word lines in non-volatile memory

A data storage device includes a non-volatile memory and a controller. The non-volatile memory includes a word line coupled to a plurality of storage elements. A method includes detecting a condition associated with a defect in the word line. A first subset of the plurality of storage elements and a second subset of the plurality of storage elements are determined based on an estimated location of the defect. The method further includes determining a first read threshold for the first subset and a second read threshold for the second subset.

Word line defect detection and handling for a data storage device

A three-dimensional memory device includes a first alternating stack of first insulating layers and first electrically conductive layers, a first memory opening fill structure extending through the first alternating stack and including a first memory film and a first vertical semiconductor channel, a joint-level electrically conductive layer overlying the first alternating stack, at least one joint-level doped semiconductor portion contacting a top surface of the first vertical semiconductor channel and located within, and electrically isolated from, the joint-level electrically conductive layer, a second alternating stack of second insulating layers and second electrically conductive layers located over the joint-level electrically conductive layer, and a second memory opening fill structure extending through the second alternating stack and including a second memory film and a second vertical semiconductor channel that is laterally surrounded by the second memory film and vertically extends into the at least one joint-level doped semiconductor portion.

Three-dimensional memory devices containing inter-tier dummy memory cells and methods of making the same

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Saratoga, CA, United States of America

Dana Lee