Altera Corporation

Lightspeed Semiconductor Corporation

Agate Logic, Inc.

Intel Corporation

Cswitch Corporation

Dana How

Herman Henry Schmit

Adi Srinivasan

Carl Ebeling

Michael David Hutton

Sean R Atsatt

Ramanand Venkata

Malcolm J Wing

Godfrey P D'Souza

Colin Neal Murphy

David Wolk Mendel

Mahesh A Iyer

Christopher F Lane

Abbas A El Gamal

Arun Jangity

Pohrong Rita Chu

Mukunda Krishnappa

Jason Golbus

Arifur Rahman

Robert Osann, Jr

Dinesh D Patil

Shridhar K Mukund

Jeffrey Erik Schulz

Suresh Subramaniam

Audrey Catherine Kertesz

Martin Langhammer

Andy Louie Lee

David Lewis

James Loran Ball

Ting Lu

Eric F Dellinger

Jay B Patel

Jeffrey Christopher Chromczak

Bee Yee Ng

Robert K Yu

Saurabh Adya

Abbas El Gamal

Eng Ling Ho

Vadim Gutnik

Douglas A Laird

Ivo J Dobbelaere

Kevin James

Dave Trossen

Robert Osann

Suresh Subramanian

An FPGA includes a number of logic elements in a core fabric. Each logic element includes a number of registers and each register includes a registered circuit path and a combinatorial circuit path. The registered and combinatorial circuit paths are in parallel. Each register includes a DFT circuit path that comprises an input in the registered circuit path and an output in the registered circuit path. The DFT circuit path is not in series with the registered circuit path and is not in series with the combinatorial circuit path. Each register includes a CE time-borrowing circuit path. Each the CE time-borrowing circuit path includes an input in the registered circuit path and an output that is coupled to the input of the registered circuit path. The CE time-borrowing circuit path is not in series with the registered circuit path and is not in series with the combinatorial circuit path.

Quick configurable universal register for a configurable integrated circuit die

Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include a master die that is coupled to one or more slave dies via inter-die package interconnects. A mixed (i.e., active and passive) interconnect redundancy scheme may be implemented to help repair potentially faulty interconnects to improve assembly yield. Interconnects that carry normal user signals may be repaired using an active redundancy scheme by selectively switching into use a spare driver block when necessary. On the other hand, interconnects that carry power-on-reset signals, initialization signals, and other critical control signals for synchronizing the operation between the master and slave dies may be supported using a passive redundancy scheme by using two or more duplicate wires for each critical signal.

Programmable integrated circuits with in-operation reconfiguration capability

Systems and methods relating to a programmable circuit. The programmable circuit includes multiple sectors. Each sector includes configurable functional blocks, configurable routing wires, configuration bits for storing configurations for the functional blocks and routing wires, and local control circuitry for interfacing with the configuration bits to configure the sector. The programmable circuit may include global control circuitry for interfacing with the local control circuitry to configure the sector. Each sector may be independently operable and/or operable in parallel with other sectors. Operating the programmable circuit may include using the local control circuitry to interface with the configurations bit and configure the sector. Additionally, operating the programmable circuit may include using the global control circuitry to interface with respective local control circuitry and configure the sector.

Programmable circuit having multiple sectors

An integrated circuit includes a signal network and a phase detector circuit. The signal network includes an adjustable delay circuit. The adjustable delay circuit is coupled at an intersection in the signal network between branches of the signal network. The signal network generates a first signal at a first leaf node of the signal network in response to a second signal. The signal network generates a third signal at a second leaf node of the signal network in response to the second signal. The phase detector circuit compares phases of the first and third signals to generate a phase detection signal. The adjustable delay circuit adjusts a delay provided to the first signal relative to the second signal to reduce a skew between the first and third signals based on the phase detection signal indicating that the first and third signals have the skew.

Techniques for signal skew compensation

Systems and methods are provided herein for providing an NoC including a configurable array of nodes, where a node of the configurable array of nodes operates in a default operating mode until a replacement operating mode is triggered. For example, when an NoC is unconfigured, a latch bank may be initialized to 'clear,' such that no routing decisions are stored. This may enable a default operating mode where routing logic updates the latches' values as needed to implement required routing behavior in a dynamic fashion until configuration is performed.

Network-on-chip with fixed and configurable functions

Systems and methods for providing a Network-On-Chip (NoC) structure on an integrated circuit for high-speed data passing. In some aspects, the NoC structure includes multiple NoC stations with a hard-IP interface having a bidirectional connection to local components of the integrated circuit. In some aspects, the NoC stations have a soft-IP interface that supports the hard-IP interface of the NoC station.

Programmable logic device with integrated network-on-chip

An integrated circuit that includes different types of embedded functional blocks such as programmable logic blocks, memory blocks, and digital signal processing (DSP) blocks is provided. At least a first portion of the functional blocks on the integrated circuit may operate at a normal data rate using a core clock signal while a second portion of the functional blocks on the integrated circuit may operate at a 2&#xd7; data rate that is double the normal data rate. To support this type of architecture, the integrated circuit may include clock generation circuitry that is capable of providing double pumped clock signals having clock pulses at rising and falling edges of the core clock signal, data concentration circuitry at the input of the 2&#xd7; functional blocks, and data spreading circuitry at the output of the 2&#xd7; functional blocks.

Integrated circuits with embedded double-clocked components

Mixed redundancy scheme for inter-die interconnects in a multichip package

Systems and methods for a low hold-time sequential input stage provide circuitry that includes a first latch element receiving a first input. The first latch element is connected to a first two-input multiplexer. The circuitry further includes a second latch element receiving a second input. The second latch element is connected to the first two-input multiplexer. The first input and the second input originate from different input cells of an input column that receive a same source signal.

Systems and methods for a low hold-time sequential input stage

Systems and methods for phase detection are disclosed. Phase alignment between first and second clock signals is detected using a comparison of outputs from a collapsible pipeline and a non-collapsible pipeline.

Systems and methods for clock alignment using pipeline stages

In server virtualization, the resources of an integrated circuit are partitioned into smaller portions, and each of these smaller portions is then operated independently. Software is used to represent the smaller portions as virtual environments. For the purpose of server virtualization, an integrated circuit may include several different circuit designs, each implemented in a secure partition in the integrated circuit. The operation of the circuit design implementations in the integrated circuit may require that each circuit design implementation can be verified as un-altered and from the respective user or owner and as having been approved by the integrated circuit owner and/or the circuit design implementation owner. The operation of the circuit design implementations in the integrated circuit may require that each circuit design implementation can be operated securely and independently of the other circuit design implementations in the integrated circuit.

Circuit design implementations in secure partitions of an integrated circuit

A clock-tree construction method for a configurable clock grid structure having a plurality of sectors and a plurality of wire segments includes defining a clock region within the clock grid structure and constructing an H-tree that has a smallest size to cover the clock region. The method further includes aligning the clock region within the H-tree, pruning the H-tree and removing an unused segment from the H-tree. The method further includes performing a tree height reduction procedure to the pruned H-tree, and generating a clock tree with a reduced size or a reduced height from the tree height reduction procedure.

Sector-based clock routing methods and apparatus

Systems and methods are provided for distributing clocks or other signals on an integrated circuit. In some aspects, one or more distributed deskewing objects are provisioned for reducing or eliminating skew while linking multiple clock distribution segments into one clock tree of an arbitrary shape and size.

Clock grid for integrated circuit

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Palo Alto, CA, United States of America

Dana How