Intel Corporation

Arizona State University

Arizona Board of Regents, a Body Corporate

Alta Devices, Inc.

Dan Wheeler Patterson

Lawrence T Clark

Matthew Eldridge

Gordon W Stoll

Nathan D Hindman

Xiaoyin Yao

Gang He

Peter D MacWilliams

Gregg Higashi

Gurbir Singh

Srivatsan Chellappa

Stephen J Strazdus

Liguang Lan

Linlin Yang

Vikram Gupta

Bindi A Prasad

David E Pettit

Peter J DesRosier

Rahul Shringarpure

Stephen H Hunt

Chandarasekaran Ramamurthy

Phil G Lee

Paul Goddu

Steve Hunt

This disclosure relates generally to computerized systems and methods of producing a physical representation of an in silico Integrated Circuit (IC) having an in silico Multi-Mode Redundant (MMR) pipeline circuit. An IC layout of the in silico IC is initially generated with the electronic design automation (EDA) program. Multi-Mode Redundant Self-Correcting Sequential State Element (MMRSCSSE) layouts are then rendered immotile while initial redundant Combinational Logic Circuit (CLC) layouts are removed from the IC layout after the MMRSCSSE layouts have been rendered immotile. By first placing the MMRSCSSE layouts and then rendering them immotile, the remaining logic can be placed again and optimized without compromising critical node spacing. As such, the described method provides for a more efficient way to create the IC layout of the in silico IC while maintaining critical node spacing.

Techniques for generating physical layouts of in silico multi mode integrated circuits

System and method of providing a photovoltaic (PV) cell with a complex via structure in the substrate that has a primary via for containing a conductive material and an overflow capture region for capturing an overflow of the conductive material from the primary via. The conductive filling in the primary via may serve as an electrical contact between the PV cell and another PV cell. The overflow capture region includes one or more recesses formed on the substrate back surface. When the conductive material overflows from the primary via, the one or more recesses can capture and confine the overflow within the boundary of the complex via structure. A recess may be a rectangular or circular trench proximate to or overlaying the primary via. The recesses may also be depressions formed by roughening the substrate back surface.

Via structures for solar cell interconnection in solar module

The disclosure relates generally to triple-redundant sequential state (TRSS) machines formed as integrated circuits on a semiconductor substrate, such as CMOS, and computerized methods and systems of designing the triple-redundant sequential state machines. Of particular focus in this disclosure are sequential state elements (SSEs) used to sample and hold bit states. The sampling and holding of bits states are synchronized by a clock signal thereby allowing for pipelining in the TRSS machines. In particular, the clock signal may oscillate between a first clock state and a second clock state to synchronize the operation of the SSE according to the timing provided by the clock states. The SSEs has a self-correcting mechanism to protect against radiation induced soft errors. The SSE may be provided in a pipeline circuit of a TRSS machine to receive and store a bit state of bit signal generated by combinational circuits within the pipeline circuit.

Sequential state elements in triple-mode redundant (TMR) state machines

The disclosure relates generally to triple-redundant sequential state (TRSS) machines formed as integrated circuits on a semiconductor substrate, such as CMOS, and computerized methods and systems of designing the triple-redundant sequential state machines. Of particular focus in this disclosure are sequential state elements (SSEs) used to sample and hold bit states. The sampling and holding of bits states are synchronized by a clock signal thereby allowing for pipelining in the TRSS machines. In particular, the clock signal may oscillate between a first clock state and a second clock state to synchronize the operation of the SSE according to the timing provided by the clock states. The SSEs have a self-correcting mechanism to protect against radiation induced soft errors. The SSE may be provided in a pipeline circuit of a TRSS machine to receive and store a bit state of bit signal generated by combinational circuits within the pipeline circuit.

Embodiments of circuits for processors with multiple redundancy techniques for mitigating radiation errors are described herein. Other embodiments and related methods and examples are also described herein.

Circuits and methods for processors with multiple redundancy techniques for mitigating radiation errors

Embodiments of circuits and methods for circuits for the detection of soft errors in cache memories are described herein. Other embodiments and related methods and examples are also described herein.

Circuits and methods for detection of soft errors in cache memories

Embodiments of circuits and method for dual redundant register files with error detection and correction mechanisms are described herein. Other embodiments and related examples are also described herein.

Circuits and methods for dual redundant register files with error detection and correction mechanisms

A system and method for parallel rendering of images are described. Image information is stored into at least one buffer for display on a plurality of display modules. A predetermined number of image units from said image information are mapped to each display module of said plurality of display modules.

System and method for parallel rendering of images

A processor system having cache array for storing virtual tag information and physical tag information and corresponding comparators associated with the array to determine cache-hits. Information from the virtual tag array and the physical tag array may be accessed together.

Snoopy virtual level 1 cache tag

An electronic component for failure detection and analysis of bus activity comprises configuration circuitry, a buffer, and read circuitry. The configuration circuitry, the buffer, the read circuitry and the bus being tracked are on the same die. The configuration circuitry identifies one or more modes, one or more triggers, and one or more responses associated with the triggers. The buffer stores transactions on a bus according to the configuration circuitry. The read circuitry reads data from the buffer. A method of tracking bus activity comprises configuring a bus activity tracking component; monitoring an interface for a trigger event; and performing associated responses upon the occurrence of the trigger event.

Method and apparatus for bus activity tracking

An apparatus and method are disclosed for providing concurrent access to first storage area and a second storage area. According to one embodiment, a device includes the first storage area. The device and the second storage area are both coupled to a first bus and are coupled together by a dedicated second bus. According to one embodiment, a snoop operation on the first storage area be preferred concurrently with a snoop operation on the second storage area.

Multi-bus access cache

A computer system having a processor-cache protocol supporting multiple cache configurations is described. The computer system has a processor having a cache control circuit to control multiple cache memory circuits. The processor including its cache control circuit is coupled to a cache bus. A second level cache memory is also coupled to the cache bus. The cache control circuit controls the second level cache by issuing commands that are executed by the second level cache.

Growing community of inventors

Scottsdale, AZ, United States of America

Dan Wheeler Patterson