Xpliant, Inc.

Marvell Asia Pte., Ltd.

Cavium, Inc.

Dan Tu

Enric Musoll

Tsahi Daniel

Avinash Sodani

Chia-Hsin Chen

Sridevi Polasanapalli

Enrique Musoll

Weihuang Wang

Guy Hutchison

Prasanna Vetrivel

Control logic circuitry stores packets in a queue in an order in which the packets are received. A head entry of the queue corresponds to an oldest packet in the order. The control logic circuitry receives flow control information corresponding to multiple target devices including at least a first target device and a second target device. The control logic circuitry determines, using the flow control information, whether the oldest packet stored in the head entry can be transferred to the first target device, and in response to determining that the oldest packet stored in the head entry cannot be transferred to the first target device, i) selects an other entry with an other packet behind the head entry according to the order, and ii) transfers the other packet to the second target device prior to transferring the oldest packet in the head entry to the first target device.

Queueing system with head-of-line block avoidance

A multi-dimensional mesh architecture is proposed to support transmitting data packets from one source to a plurality of destinations in multicasting or broadcasting modes. Each data packet to be transmitted to the destinations carries a destination mask, wherein each bit in the destination mask represents a corresponding destination processing block in the mesh architecture the data packet is sent to. The data packet traverses through the mesh architecture based on a routing scheme, wherein the data packet first traverses in a first direction across a first set of processing blocks and then traverses in a second direction across a second set of processing blocks to the first destination. During the process, the data packet is only replicated when it reaches a splitting processing block where the paths to different destinations diverge. The original and the replicated data packets are then routed in different directions until they reach their respective destinations.

System and methods for mesh architecture for high bandwidth multicast and broadcast network

An on-chip crossbar of a network switch comprising a central arbitration component configured to allocate packet data requests received from destination port groups to memory banks. The on-chip crossbar further comprises a Benes routing network comprising a forward network having a plurality of pipelined forward routing stages and a reverse network, wherein the Benes routing network retrieves the packet data from the memory banks coupled to input of the Benes routing network and route the packet data to the port groups coupled to output of the Benes routing network. The on-chip crossbar further comprises a plurality of stage routing control units each associated with one of the forward routing stages and configured to generate and provide a plurality of node control signals to control routing of the packet data through the forward routing stages to avoid contention between the packet data retrieved from different memory banks at the same time.

Apparatus and method for on-chip crossbar design in a network switch using benes network

A packet processor includes a header processor and a packet memory. A receive direct memory access block is configured to receive a packet with a header and a payload and to route the header to the header processor and to route the payload to the packet memory such that the header processor begins processing of the header while the payload is loaded into packet memory.

Method for storing and retrieving packets in high bandwidth and low latency packet processing devices

A packet processor has a packet memory manager configured to store a page walk link list, receive a descriptor and initiate a page walk through the page walk link list in response to the descriptor and without a prompt from transmit direct memory access circuitry. The packet memory manager is configured to receive an indicator of a single page packet and read a new packet in response to the indicator without waiting to obtain page state associated with the page of the single page packet.

Apparatus and method for accelerated page link list processing in a packet processor operating at wirespeed

A method of processing packets includes receiving packets and assigning the packets to different pages, where each page represents a fixed amount of memory. The different pages are distributed to different pools, where each pool has a unique mapping to banks, and where each bank is a set of memory resources. The different pages from the different pools are assigned to different banks in accordance with the unique mapping.

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San Bruno, CA, United States of America

Dan Tu