Hewlett-packard Development Company, L.P.

Dan Tormey

Joe Bolding

Gerald Everett

Bjorn Helgaas

A system and method for protecting a defined range of hardware addresses or a defined set of processor instructions from being accessed or executed by unauthorized software modules. Abstraction layer code is given a range of software addresses that are permitted to access the protected addresses or execute the instructions. Authorized accesses must utilize service routines provided by the abstraction layer code. When an attempted access to a protected hardware address is detected, it is determined whether the access is from the abstraction layer code. If so, the access is permitted. If not, the access is prohibited, and an error message is generated. A basic set of authorized processor instructions and an extended set of processor instructions may be defined for a reference platform. Execution of processor instructions in the extended set is limited to authorized abstraction layers. Otherwise, the attempted execution is prohibited, and an error message is generated.

System and method of limiting access to protected hardware addresses and processor instructions

A system and method for managing utilization in a stack. A stack base and a stack pointer are initialized for the stack. Upon fetching a program instruction to be executed in a computing environment, a determination is made if the program instruction involves accessing a location within a valid stack range that is defined by a high water mark operable to identify the stack pointer's farthest location from the stack base. The farthest location is indicative of how far the stack has grown at any time during the program's execution. A warning may be provided upon determining that the location to be accessed is not within the valid stack range.

Stack utilization management system and method for a single-stack arrangement

A system and method for setting and executing breakpoints utilized for debugging program code. A user interface (UI) stores breakpoint addresses in a breakpoint table within a central processing unit (CPU). Multiple breakpoint addresses may be stored in the table as a range of addresses in a single entry. A flag indicates whether each stored address or address range is a physical or virtual address. When executing the program code on the CPU, an instruction core requests from an instruction cache, an instruction associated with a particular address. The cache first determines from the breakpoint table within the CPU whether there is a breakpoint associated with the particular address. If so, the cache returns control to the UI. Otherwise, the cache goes out to a coherency controller to fetch the instruction from memory.

System and method for setting and executing breakpoints

A system and method for synchronizing processors simulated in an architectural simulator for a multiprocessor environment. A synchronous breakpoint is set at a predetermined address location and a code portion targeted for execution on the target multiprocessor environment is launched on the simulator from a fixed location. Upon automatically stepping through a list of processors initialized in the simulator until each of the processors reaches the synchronous breakpoint, run control is returned to the user only after all processors have achieved a synchronous state. Debug operations may ensue thereafter by utilizing a debugger integrated with the architectural simulator.

Synchronous breakpoint system and method

A system and method for managing utilization in a unidirectional stack. An application programming interface (API) is provided for facilitating user interaction with a stack management system associated with a computing environment such as an architectural simulator. The unidirectional stack is initialized via the API with respect to a fixed stack marker boundary, a stack base and a stack pointer. A high water mark is maintained for tracking the stack pointer's farthest location from the stack base during the execution of a program. When a program instruction is operable to access a stack location, one or more validity rules are applied to determine if the access operation is permissible. Where the program instruction is operable to modify the stack pointer, another set of validity rules are applied to determine if the stack pointer operation is permissible. User warning and optional return of program control are available when an invalid access operation or stack pointer operation is attempted.

A system and method for managing stack utilization in a two-stack arrangement wherein the stacks are operable to grow towards each other. An application programming interface (API) is provided for facilitating user interaction with a stack management system associated with a computing environment such as an architectural simulator. Each of two stacks is initialized via the API with a stack base, a growth direction indicator and a stack pointer. High water marks are maintained for tracking each stack pointer's farthest location from the respective stack base during the execution of a program. When a program instruction is operable to access a location in either of the stacks, one or more validity rules are applied to determine if the access operation is permissible. Where the program instruction is operable to modify either of the stack pointers, another set of validity rules are applied to determine if the stack pointer operation is permissible. User warning and optional return of program control are available when an invalid access operation or stack pointer operation is attempted.

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Richardson, TX, United States of America

Dan Tormey