Unisys Corporation

Dan T Tran

Theodore C White

Jayesh V Sheth

Paul B Ricci

Wayne C Datwyler

Long V Ha

Richard A Cowgill

Kha Nguyen

A multi-module network having dual system busses using a common bus protocol which supports processor modules using a store-through cache memory and processor modules using a non-store-through cache memory which includes interface modules including a spy unit for maintaining cache coherency and arbiter modules so that any particular module is not starved out. A maintenance processor organizes the network as a joined system where both the store-through and non-store through processor units can utilize either one of the dual system busses or a split system where one bus is dedicated to the store-through processor units and one bus is dedicated to the non-store through processor units.

Dual bus system with multiple processors having data coherency

Apparatus and method are provided for preventing access to a memory location while that memory location is being modified, updated, etc. When a peripheral device wishes to accomplish such a change at a memory location, it provides the changed data and its intended memory address to an input/output unit. The input/output unit includes a plurality of separately controlled multiplexers, the number of multiplexers being preferably selected to correspond to the size (in bits) of a memory data word or packet divided by the size (in bits) of a peripheral data word. The input/output unit reads the data at the requested memory location into an input buffer, combines the portions of that data not to be modified with the data provided by the peripheral, and sends the result back to the same memory location. During this Read-Modify-Write operation, the input/output unit also monitors the system bus for any attempts or requests to read data from, or write data to, the memory address for which the Read-Modify-Write operation is being performed. In such event, a signal is sent to the module making such attempt or request, asking or telling that module to wait. That signal is removed when that Read-Modify-Write operation is completed.

Information processing system having multiple modules and a memory on a

The logic circuitry of an IC chip is connected to JTAG register chains which hold state information on each portion of the logic circuitry therein. A JTAG Tracker Module is connected to the controls of each of the JTAG register chains enabling a programmer-operator to read the present state of each JTAG register chain and enabling a readout of the logic circuits condition in a single clock period.

Method and system for tracking the state of each one of multiple JTAG

A single chip data path gate array interface links a central processing unit, operating at a first clock rate and single word protocol, to dual system busses operating at a second clock rate and multiple-word protocol. The data path interface holds command, data and message registers, controlled by external logic, in an input channel pathway and an output channel pathway. The interface chip is basically limited to registers and multiplexers making it flexible for use in different architectures such as both Store-Through and Non-Store-Through cache protocols. In addition, such a simplified chip is simple to fabricate and to maintain free of defects.

Dual bus adaptable data path interface system

A network of digital modules having store-through and non-store-through cache memories, is provided with intercommunication capability by means of two sets of system busses each of which are replicates of each other. The system busses provide a higher throughput by both being available to each of the digital modules so that a requesting digital module can alternately use a second system bus if the first system bus happens to be busy. Failure of one system bus will allocate transmission service to the second operating system bus thus providing redundancy. Alternatively, each of the system busses can be isolated for partitioning the digital modules into two different operating systems which are independent of each other.

Configurable network using dual system busses with common protocol

An error logging system where errors are captured on dual system busses operating at a lower clock rate (16 MHz) than the processor which receives the error information. The system functions to substantially reduce the loads on the processor in addition to maximizing the use of the system bus drivers which are pin-constrained. The processor operates at a higher clock rate (32 MHz). Processor commands to read error data from an error log register are synchronized down to the 16 MHz rate, then enabled onto a processor bus after a second synchronization operation back to the higher (32 MHz) rate. Provision is made for identifying several different types of error categories. An expandable error log register system is provided which uses selected bit positions to identify types of errors logged to the processor which also enables expansitivity for adding in future types of errors into the error logging system and renders compatibility for a processor operating at first clock rate with error data sensed at a second clock rate.

Error logging system with clock rate translation

A memory module is used in multiples on a bus in a data processing system. Each memory module comprises a plurality of storage cells, an input circuit for receiving a read command and a read address from the bus, and a compare circuit which generates a match signal when the read address is within a selectable address range for the storage cells. Also, the module further includes: a control circuit, coupled to the compare circuit, which responds to the match signal by almost always executing the read command in a small time interval on the bus and occasionally executing the read command in a long time interval. Further, the module includes a bus transmit circuit, coupled to the control circuit, for sending a control signal on the bus if the control circuit selects the long time interval. Also, the module includes an error circuit, coupled to the control circuit and the bus, for setting an error flag if the control circuit selects the short time interval and, during that short time interval, the control signal is detected on the bus from another module in the memory system.

Memory module with address error detection

A User bus lockout prevention mechanism for use in a time-shared busy multiple bus User, computer architecture where bus Users include private cache systems which perform a cache cycle when a WRITE TO MEMORY instruction occurs on the bus to determine if data cached from main memory has been overwritten in main memory. A User can be locked out from use of the bus if a synchronism occurs between repetative cache cycles and periodicity of the Retry mechanism of the User. Bus lockout is prevented by the User with the cache issuing an INHIBIT WRITE to the bus when a cache cycle is being performed. Other Users inhibit issuing WRITE TO MEMORY requests to the bus until the INHIBIT WRITE signal terminates. Bus requests other than a write request may be issued to the bus during INHIBIT WRITE.

Inhibit write apparatus and method for preventing bus lockout

A User bus lockout prevention mechanism for use in a time-shared bus, multiple bus User, computer architecture where bus Users have private cache systems which perform a cache cycle when a WRITE TO MEMORY instruction occurs on the bus to determine if data cached from main memory has been overwritten in main memory. A User can be locked out from use of the bus if a synchronism occurs between repetitive cache cycles and periodicity of the request Retry mechanism of the User. Bus lockout is prevented by controlling the Retry mechanism of the User to retry requests in accordance with a sequence of varying retry wait intervals. The sequence comprises bursts of short wait intervals interleaved with long wait intervals, the sequence beginning with a burst of short wait intervals. The wait interval durations of the first and second occurring bursts are interleaved with respect to each other. The second occurring long wait is longer than the first occurring long wait. The sequence is terminated upon bus grant.

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Laguna Niguel, CA, United States of America

Dan T Tran