Cadence Design Systems, Inc.

Dan Richard Kaiser

Aaron Mitchell Spratt

William Scott Cranston

Steven Guy Esposito

Junwei Hou

Jonathan Lee DeKock

The present disclosure relates to defining and processing hardware description language (HDL) groups. Embodiments may include mapping, using a processor, a set of tool-specific objects into a group graph with one or more groups. Embodiments may also include generating a search order associated with each group. The search order associated with each group may be based upon the hierarchical design configuration of the group graph. Embodiments may further include identifying undefined references from within a first group within the group graph and binding defined references from within the first group to electronic circuit design components. Embodiments may include identifying the undefined references from within a second group within the group graph. The second group may be selected based upon the undefined references and the search order associated with the first group.

System and method for hierarchical library searching

The present disclosure relates to a computer-implemented method for simulating an analog and mixed-signal circuit design having a digital circuit segment connected to an analog circuit segment at a connection point. The method may include inserting a bidirectional interface element at the connection point located between the digital circuit segment and the analog circuit segment. The method may further include splitting the digital circuit segment into a plurality of transistor network models to provide for bidirectional transfer of data between the analog circuit segment and the digital circuit segment.

System, method, and computer program product for simulating a mixed signal circuit design

A method and system for resolving circuit and network parameters. A circuit evaluation system includes a plurality of nodes and a plurality of resolution devices. Each node is connected to a resolution device via a bi-directional connection, and at least one node is configured to receive data from an input. Each enabling element is associated with a resolution device. Enabling elements that are associated with resolution devices that are connected to nodes that are configured to receive input data are activated, thereby enabling certain resolution devices. The enabled resolution devices are executed using data in the nodes that are connected to the enabled resolution devices. Iterations of executing resolution devices are performed until stable node values are determined.

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Traverse City, MI, United States of America

Dan Richard Kaiser