International Business Machines Corporation

Globalfoundries Inc.

Samsung Electronics Co., Ltd.

Globalfoundries U.S. Inc.

Dan Moy

Chandrasekharan Kothandaraman

Norman Whitelaw Robson

John Matthew Safran

Rajiv V Joshi

Devendra K Sadana

Jack Allan Mandelman

Junjing Bao

Yan Zun Li

Toshiaki Kirihata

Choon-Sik Oh

Carl John Radens

Ghavam G Shahidi

William R Tonti

Toshiharu Furukawa

Ping-Chuan Wang

Elbert Emin Huang

Andrew Herbert Simon

Ronald G Filippi

Griselda Bonilla

Tze-Chiang Chen

Gary Bela Bronner

Naftali Eliahu Lustig

Kaushik Chanda

Stephan Grunow

Kenneth Jay Stein

Samuel S Choi

Deok-Kee Kim

Kenneth John Giewont

Byeongju Park

Maurice Heathcote Norcott

Junedong Lee

Bijan Davari

Scott R Stiffler

O Sung Kwon

Brian W Messenger

Siegfried Lutz Maurer

Xiaoqiang Zhang

Stephen Wu

Derek H Leu

Neena Garg

Stephen Richard Fox

Kihwang Son

Peter Wang

Edwin Soler

Gabriel Chiulli

Lawrence Alfred Clevenger

Effendi Leobandung

Louis L Hsu

Christian Lavoie

Zhong-Xiang He

Robert Russell Robison

Chengwen Pei

Douglas Duane Coolbaugh

Subramanian Srikanteswara Iyer

Kai D Feng

Herbert Lei Ho

Robert Mark Rassel

Zhengwen O Li

Ebenezer E Eshun

Viraj Yashawant Sardesai

James A Culp

Darren Lane Anand

Werner A Rausch

Fariborz Assaderaghi

Mark B Ritter

Hongwen Yan

Keith Howard Tabakman

James M Harper

Young Hoon Kwark

Ephrem G Gebreselasie

Jeffrey John Welser

Richard Andre Wachnik

Dennis L Rogers

Stephen Bruce Brodsky

Pinping Sun

Faraz Khan

Xiang Chen

Shahrnaz Motakef

Robert Katz

The present disclosure generally relates to semiconductor structures and, more particularly, to charge trap memory devices and methods of manufacture and operation. The semiconductor memory includes: a charge trap transistor comprising a gate structure, a source region and a drain region; and a self-heating circuit which selectively applies an alternating bias direction between the source region and the drain region of the charge trap transistor to provide an erase operation or a programming operation of the charge trap transistor.

Charge trap memory devices

A BEOL e-fuse is disclosed which reliably blows in the via and can be formed even in the tightest pitch BEOL layers. The BEOL e-fuse can be formed utilizing a line first dual damascene process to create a sub-lithographic via to be the programmable link of the e-fuse. The sub-lithographic via can be patterned using standard lithography and the cross section of the via can be tuned to match the target programming current.

Back-end electrically programmable fuse

A system and method of operating a twin-transistor, multi-time programmable memory (MTPM) memory cell that ensures accurate reproducibility of bit values read after each of write cycle. Each multi-time programmable memory cell includes a series connection of a first transistor and a second transistor. The method includes writing, using a write circuit at select memory cell locations, initial bit values to one or more select memory cells. Then, using the write circuit, a rebalancing of a state of a parameter associated with one or more the first transistor or second transistor, at each the select memory cell, is performed. Then, an erasing cycle is performed, at each the rebalanced select memory cell, the written initial bit value. In one embodiment, the erasing cycle may first be performed prior to rebalancing. The rebalancing and erasing are to be performed prior to each bit value write cycle.

Rebalancing in twin cell memory schemes to enable multiple writes

The present disclosure generally provides for an e-fuse structure and corresponding method for fusing the same and monitoring material leakage. The e-fuse structure can include a metal dummy structure and an electrical fuse link substantially aligned with a portion of the metal dummy structure, wherein the metal dummy structure cools at least part of the electrical fuse link in response to an electric current passing through the electrical fuse link.

E-fuse structure with methods of fusing the same and monitoring material leakage

A capacitor structure can include a parallel connection of a plurality of trench capacitors. First nodes of the plurality of trench capacitors are electrically tied to provide a first node of the capacitor structure. Second nodes of the plurality of trench capacitors are electrically tied together through at least one programmable electrical connection at a second node of the capacitor structure. Each programmable electrical connection can include at least one of a programmable electrical fuse and a field effect transistor, and can disconnect a corresponding trench capacitor temporarily or permanently. The total capacitance of the capacitor structure can be tuned by programming, temporarily or permanently, the at least one programmable electrical connection.

Precision trench capacitor

A method including forming a fuse link after a first fuse contact and a second fuse contact. The fuse link is in direct contact with both the first fuse contact and the second fuse contact. Embodiments of the invention provide an e-fuse that is capable of being connected to a device either through back end of line or by a long contact allowing for sufficient separation between the e-fuse and the device.

Electrical fuse with bottom contacts

An electronic fuse structure including a first Mmetal comprising a conductive cap, an Mmetal located above the Mmetal, wherein the Mmetal does not comprise a conductive cap, and a via, wherein the via electrically connects the Mmetal to the Mmetal in a vertical orientation.

Vertical electronic fuse

A semiconductor structure and method of manufacturing the same are provided. The semiconductor device includes an enhanced performance electrical fuse formed in a polysilicon fin using a trench silicide process. In one embodiment, at least one semiconductor fin is formed on a dielectric layer present on the surface of a semiconductor substrate. An isolation layer may be formed over the exposed portions of the dielectric layer and the at least one semiconductor fin. At least two contact vias may be formed through the isolation layer to expose the top surface of the semiconductor fin. A continuous silicide may be formed on and substantially below the exposed surfaces of the semiconductor fin extending laterally at least between the at least two contact vias to form an electronic fuse (eFuse). In another embodiment, the at least one semiconductor fin may be subjected to ion implantation to facilitate the formation of silicide.

Fin eFuse formed by trench silicide process

An embedded Multi-Time-Read-Only-Memory having a (MOSFET) cells' array having an initial threshold voltage (VT) including the MOSFETs arranged in a row and column matrix, having gates in each row coupled to a wordline (WL) running in a first direction and sources in each one of the columns coupled to a bitline (BL) running in a second direction; creating two dimensional meshed source line network running in the first and second directions, in a standby state, wherein BLs and MSLN are at a voltage (VDD), and the WLs are at ground; storing a data bit by trapping charges in a dielectric of a target MOSFET, VTof target MOSFET increasing to another voltage (VT) by a predetermined amount (&#x394;VT); reading a data bit by using the MOSFET threshold voltage having one of VTor VTto determine a trapped or de-trapped charge state, and resetting the data bit to a de-trapped state by de-trapping the charge.

Embedded charge trap multi-time-programmable-read-only-memory for high performance logic technology

Method of forming vertical electronic fuse interconnect structures including a conductive cap

A fabrication method for fabricating an electrically programmable fuse method includes depositing a polysilicon layer on a substrate, patterning an anode contact region, a cathode contact region and a fuse link conductively connecting the cathode contact region with the anode contact region, which is programmable by applying a programming current, depositing a silicide layer on the polysilicon layer, and forming a plurality of anisometric contacts on the silicide layer of the cathode contact region and the anode contact region in a predetermined configuration, respectively.

Electrically programmable fuse using anisometric contacts and fabrication method

An antifuse has first and second semiconductor regions having one conductivity type and a third semiconductor region therebetween having an opposite conductivity type. A conductive region contacting the first region has a long dimension in a second direction transverse to the direction of a long dimension of a gate. An antifuse anode is spaced apart from the first region in the second direction and a contact is connected with the second region. Applying a programming voltage between the anode and the contact with gate bias sufficient to fully turn on field effect transistor operation of the antifuse heats the first region to drive a dopant outwardly, causing an edge of the first region to move closer to an edge of the second region and reduce electrical resistance between the first and second regions by an one or more orders of magnitude.

Secure anti-fuse with low voltage programming through localized diffusion heating

An electrically programmable fuse that includes an anode contact region and a cathode contact region are formed of a polysilicon layer having a silicide layer formed thereon, and a fuse link conductively connecting the cathode contact region with the anode contact region, which is programmable by applying a programming current, and a plurality of anisometric contacts formed on the silicide layer of the cathode contact region or on both the silicide layer of the cathode contact region and the anode contact region in a predetermined configuration, respectively.

Growing community of inventors

Bethel, CT, United States of America

Dan Moy