Qualcomm Incorporated

Nvidia Corporation

Mediatek Singapore Pte. Ltd.

Qst Holdings LLC

Qst Holding, LLC

Dan MingLun Chuang

Bicheng William Wu

Paul L Master

Eugene B Hogenauer

Chun Yu

Chia-Yuan Teng

Gokce Dane

Raghavendra Nagaraj

Steve Hengchen Hsu

Michael Hugh Anderson

Geoffrey Shippee

Vladan Andrijanic

Rajat Rajinderkumar Dhawan

Rojit Jacob

Bjorn Freeman-Benson

Che Fang

Hsiao-Han Ma

Yiu-Wing Leung

Chia-An Lin

Wei-Lun Hung

Bjorn Freeman Benson

A device protects data dependency for memory access. The device includes a memory and a processor. The processor executes memory access instructions including load instructions and store instructions. The processor includes load circuitry to execute the load instructions; and store circuitry to execute the store instructions. Each memory access instruction includes a token index field containing a token index that associates the memory access instruction with a memory location. The processor further includes dispatch circuitry to dispatch instructions to the load circuitry and the store circuitry; and a token registry to record used token indices according to token index fields in the memory access instructions dispatched by the dispatch circuitry.

Token-based data dependency protection for memory access

A method for video processing may include receiving video data units, and compressing the video data units to generate compressed video data units that have a variable size. The method may also include storing the compressed video data units contiguously in a memory in memory segments that have a fixed size, where the size of at least one of the compressed video data units is indivisible by the fixed size of the memory segments, and where a portion of the indivisible compressed video data unit is stored with a portion of another compressed video data unit in one of the memory segments. The method may also include determining data storage information associated with the compressed video data units, and storing the data storage information in the memory. A system may have a video processing architecture designed to support the method.

Video processing architecture

A 3D graphics pipeline includes a prefetch mechanism that feeds a cache of depth tiles. The prefetch mechanism may be predictive, using triangle geometry information from previous pipeline stages to pre-charge the cache, thereby allowing for an increase in memory bandwidth efficiency. A z-value compression technique may be optionally utilized to allow for a further reduction in power consumption and memory bandwidth.

Tiled prefetched and cached depth buffer

A method, system and program are provided for development of an adaptive computing integrated circuit and corresponding configuration information, in which the configuration information provides an operating mode to the adaptive computing integrated circuit. The exemplary system includes a scheduler, a memory, and a compiler. The scheduler is capable of scheduling a selected algorithm with a plurality of adaptive computing descriptive objects to produce a scheduled algorithm and a selected adaptive computing circuit version. The memory is utilized to store the plurality of adaptive computing descriptive objects and a plurality of adaptive computing circuit versions generated during the scheduling process. The selected adaptive computing circuit version is converted into a hardware description language, for fabrication into the adaptive computing integrated circuit. The compiler generates the configuration information, from the scheduled algorithm and the selected adaptive computing circuit version, for the performance of the algorithm by the adaptive computing integrated circuit. In the exemplary embodiments, multiple versions of configuration information may be generated, for different circuit versions, different feature sets, different operating conditions, and different operating modes.

Method, system and program for developing and scheduling adaptive integrated circuitry and corresponding control or configuration information

The present invention provides an adaptive computing engine (ACE) that includes processing nodes having different capabilities such as arithmetic nodes, bit-manipulation nodes, finite state machine nodes, input/output nodes and a programmable scalar node (PSN). In accordance with one embodiment of the present invention, a common architecture is adaptable to function in either a kernel node, or k-node, or as general purpose RISC node. The k-node acts as a system controller responsible for adapting other nodes to perform selected functions. As a RISC node, the PSN is configured to perform computationally intensive applications such as signal processing.

System and method using embedded microprocessor as a node in an adaptable computing machine

Method, system and program for developing and scheduling adaptive integrated circuity and corresponding control or configuration information

A system whereby a data flow language written in relatively high-level description is compiled to a hardware definition. The hardware definition is then used to configure data flow in a target processing system at execution time, or run time. In a preferred embodiment, the target processing system includes a Reduced-Instruction Set Computer (RISC) processor in communication with a finite state machine (FSM), shared memory, on-board memory, and other resources. The FSM is primarily used for accelerating matrix operations and is considered the target machine to be configured according to the dataflow definition. The RISC processor serves as a co-processor to an external central processing unit (CPU) that is a host processor for executing application code. Other embodiments can use aspects of the invention in any other processing architecture. A dataflow language is used to define interconnections among hardware elements in the matrix datapath and controlled by FSM at run time and, thus, to determine hardware functionality at run time. The interconnectivity between the matrix datapath components, elements or resources, is capable of changing every clock cycle to optimize preferred calculations. The dataflow language is used to describe the optimized functions to an application programmer. The dataflow language is also compiled to a hardware definition that is used to create aspects of the desired functionality in silicon.

Digital processing architecture using compiled dataflow definition

Growing community of inventors

San Diego, CA, United States of America

Dan MingLun Chuang