International Business Machines Corporation

Other

Dan Marvin Neal

Richard Allen Kelley

Steven Mark Thurber

Edward John Silha

Paul Lee Clouser

A collapsible privacy shelter includes an upper section, lower section, and roof section. The lower section includes a back wall, a pair of side walls pivotally connected to the back wall of the lower section and are operable to fold inward, a front wall pivotally connected to the plurality of side walls of the lower section, and a door pivotally connected to the front wall of the lower section. The upper section includes a back wall disposed on an edge of the back wall of the lower section and operable to engage the back wall of the lower section, a pair of opposing side walls pivotally connected to the back wall of the upper section and operable to fold inward and each operable to engage a corresponding side wall of the lower section, a front wall pivotally connected to the plurality of side walls of the upper section and operable to engage the front wall of the lower section, and a door pivotally connected to the upstanding front wall of the upper section and operable to engage the door of the lower section. The roof section includes a roof operable to engage an upper portion of the upper section.

Collapsible privacy shelter

The present invention relates to an apparatus and method for enhancing the differential signaling speed performance of a PCI bus within a data processing system. In particular it involves the connectors employed with PCI bus architecture. The present invention involves providing improved connectors employed in a PCI bus architecture. These are Split Pin and Split Via connectors which provide significantly higher frequency and higher frequency capability to the board level.

Method and apparatus for high speed differential signaling, employing split pin connectors and split via technology

A method of providing an interconnection between one or more peripheral devices and a system bus of a computer system selectively establishes and removes a connection from a primary peripheral bus to a secondary peripheral buses, and determines a target from among the one or more peripheral devices when a bus bridge is a master of the primary peripheral bus, using an address decoder. Access to and from the primary peripheral bus is controlled using an arbiter to select a master for the primary peripheral bus from among the one or more peripheral devices, to allow both (i) selective establishing and removing of a connection from the primary peripheral bus to one of the secondary peripheral buses in response to the selection of the master, and (ii) isolating of the master prior to establishing the connection to the secondary peripheral bus. Hot Plug Control Logic and Switch Control Logic in conjunction with the arbiter allows Hot Plug support along with the expanded slot environment.

Method and system for providing hot plug of adapter cards in an expanded slot environment

A method of providing an interconnection between one or more peripheral devices and a system bus of a computer system selectively establishes and removes a connection from a primary peripheral bus to a secondary peripheral buses, and determines a target from among the one or more peripheral devices when a bus bridge is a master of the primary peripheral bus, using an address decoder. Access to and from the primary peripheral bus is controlled using an arbiter to select a master for the primary peripheral bus from among the one or more peripheral devices, to allow both (i) selective establishing and removing of a connection from the primary peripheral bus to one of the secondary peripheral buses in response to the selection of the master, and (ii) isolating of the master prior to establishing the connection to the secondary peripheral bus.

Method and system for PCI slot expansion via electrical isolation

Method and system for providing peer-to-peer control in an expanded slot environment using a bridge as an agent for controlling peripheral device

A data processing system includes a host processor, a number of peripheral devices, and one or more bridges which may connect between the host, peripheral devices and other hosts or peripheral devices such as in a network. Each bus to bus bridge connects between a primary bus and a secondary bus wherein for the purpose of clarity, the primary bus will be considered as the source for outbound transactions and the destination for inbound transactions and the secondary bus would be considered the destination for outbound transactions and the source for inbound transactions. Each bus to bus bridge includes an outbound data path, an inbound data path, and a control mechanism. The outbound data path includes a queued buffer for storing transactions in order of receipt from the primary bus where the requests in the queued buffer may be mixed as between read requests and write transactions, the outbound path also includes a number of parallel buffers for storing read reply data and address information. The inbound path is a minor image of the outbound path with read requests and write requests being stored in a sequential buffer and read replies being stored in a number of parallel buffers. Both the inbound path and the outbound path in the bus to bus bridge are controlled by a state machine which takes into consideration activity in both directions and permits or inhibits bypass transactions.

Growing community of inventors

Round Rock, TX, United States of America

Dan Marvin Neal