International Business Machines Corporation

Boe Technology Group Co., Ltd.

Lsi Corporation

Beijing Xiaomi Mobile Software Co., Ltd.

Xilinx, Inc.

Avago Technologies General IP (singapore) Pte. Ltd.

Globalfoundries U.S. Inc.

Hefei Boe Optoelectronics Technology Co., Ltd.

General Electric Company

Globalfoundries Inc.

Dow Global Technolgoies LLC

Rohm and Haas Company

Chengdu Boe Optoelectronics Technology Co., Ltd.

Ge Precision Healthcare LLC

Avago Technologies International Sales Pte. Limited

Dan Liu

Shaohua Yang

Peng Wang

Yang Liu

Yong Qing Lu

Zhongsheng Jiang

Zongwang Li

Yang Han

Chung-Li Wang

Bodo Hoppe

Xu Zhang

Wei Zhang

Lei Zhang

Yuan Wx Li

Ning Zhang

Xuebin Wu

Xueli Wang

Luciano Lavagno

Xuan Li

Duo Chen

Changjun Zhang

Gang Wang

Ting Wang

Ming Wang

Bo Zhang

Bin Xu

Rui Wang

Bruce Alexander Wilson

Xin Jin

Guosheng Li

Xiao Liang Hu

Yu Chen

Yong Wang

Yu Wang

Qi Chen

Ling Li

Li Ni Zhang

Kaixuan Wang

Hem C Neema

Xu Wu

Xiao Ping Guo

Zhonghao Huang

Xiangting Dong

Qingwei Zhang

Tiejun Liu

Sheng Zhang

Tongmin Liu

Yufei Li

Guang Yu

Jun Tao

Qi Zuo

Yong Feng Pan

Amin Li

Sujing Li

Chaojie Dang

Yan Ying

Yang L Liu

Peng Fei Gou

Kaitlyn T Nguyen

Hanqing Zhao

Mingming Zhang

Lukun Zhai

Jialin Feng

Han Liu

Hua Zhao

Jianghui Zhan

Dawei Xiong

Jiang Zhu

Zhi Juan Gong

Ning Zhao

Mao Li

Hongchao He

Chao Yin

Yoon Liong Liow

Bingjie Zhao

Xun Zhang

Keke Liu

Maokun Tian

Wenjuan Zhang

Jingwei Zhang

Yongji Long

Shiyu Li

Yanling Qu

Han Lv

Jun Han

Yuxi Dong

Ruilin Wang

Run Gao

Dingdong Song

Wenjuan Mei

Xun Gu

Jian Jiao

Yifan Liu

Xuguang Sun

Bin Hou

De Xian Li

Gai Liu

Baochao Li

Xiao Dong Yan

Chengjun Qi

Inter-kernel dataflow analysis and deadlock detection includes, for each kernel of a plurality of kernels of a design, including, using computer hardware, a signal for the kernel that is asserted in response to all processes inside the kernel stalling, wherein the plurality of kernels form a strongly connected component. For each kernel of the plurality of kernels, the signal is asserted during operation of the design in response to each process in the kernel stalling. A notification is generated indicating that the strongly connected component is deadlocked in response to each kernel of the strongly connected component asserting the signal.

Inter-kernel dataflow analysis and deadlock detection

A method of interfacing a discrete digital workshop information system is provided, where the information system includes mutual integration among product lifecycle management (PLM), enterprise resource planning (ERP), a manufacturing execution system (MES), an energy management system (EMS), and a warehouse management system (WMS) of a finished product. A method of interfacing based on a data dictionary fusing different function datasets is proposed to solve the problems of a current discrete industry information system, such as single in function, a small amount of integrated information, a large number of 'information islands' existing, incapable of achieving full-process informatization management and control, difficulty in product quality tracing and the like. By the method, it is possible to realize flexible production in a discrete manufacturing industry, precise management and control of a production process, significant improvement in product quality and significant reduction in operating costs.

Method of interfacing discrete digital workshop information system

A security defending method, a coprocessor, and a processing apparatus are disclosed. The security defending method is applicable in a coprocessor, including: receiving a jump destination encryption request for the operation task; using mask configuration to perform first mask processing on the first jump destination address value to obtain a first intermediate jump destination address value; performing an authentication operation based on the first jump destination storage address, a key reference value corresponding to the operation task and the first intermediate jump destination address value, to obtain a first encryption result value; using the mask configuration to perform second mask processing on the first encryption result value to obtain a first intermediate encryption result value; performing an authentication operation on the first intermediate encryption result value and the first jump destination address value to obtain a first encryption jump destination address value.

Security defending method, coprocessor, and processing apparatus

The invention relates to a KRAS mutant protein inhibitor shown as formula (I), a composition containing the inhibitor and the use thereof.

KRAS mutant protein inhibitors

Amplifier devices includes a first amplifier connected to receive an input voltage. The first amplifier outputs an internal voltage. These structures also include a second amplifier having an input node connected to receive the internal voltage and an output node outputting an output voltage. A resistive feedback loop is connected to the input node and the output node of the second amplifier. A first cross-coupled bandwidth boosting stage is connected to the input node of the second amplifier and a second cross-coupled bandwidth boosting stage connected to the output node of the second amplifier. The cross-coupled bandwidth boosting stages form a distributed differential positive feedback structure.

Amplifier having distributed differential positive feedback

Apparatuses include (among other components) a first gain device connected to receive an initial voltage, a second gain device in series with the first gain device and connected to receive output of the first gain device, differential gain devices connected to receive outputs from the first gain device and the second gain device (the differential gain devices provide opposite voltage outputs from the apparatus) and high-frequency compensation feed-forward paths connected to the first gain device and the second gain device.

Single-to-differential converter

A line laser module, including: a module body; a first image capturing assembly, provided at the module body and comprising a first camera, at least one laser emitter and a first image processing module, wherein the at least one laser emitter is provided adjacent to the first camera and configured to emit a line laser with a linear projection toward outside of the module body, the first camera is configured to capture a first environment image containing the line laser, and the first image processing module is configured to acquire obstacle distance information based on the first environment image; and a second image capturing assembly, comprising a second camera and a second image processing module, wherein the second camera is configured to capture a second environment image, and the second image processing module is configured to acquire obstacle type information based on the second environment image.

Line laser module and autonomous mobile device

A clock control method, apparatus, and device, and a storage medium. By the method, timing optimization of bidirectional data communication between a server mainboard and a Peripheral Component Interconnect express (PCIe) expansion board is relatively implemented, and the occurrence of a situation where in any data communication direction between the server mainboard and the PCIe expansion board, data transmitted by the initiating end at a given high-level moment does not reach the receiving end at a next high-level moment may be prevented, thus ensuring the reliability of communication between the server mainboard and the PCIe expansion board. In addition, the present application further provides a clock control apparatus and device, and a storage medium, and the beneficial effects are as stated above.

Clock control method, apparatus, and device, and storage medium

An array substrate includes a base substrate, a light-shielding pattern, a buffer pattern, an active layer, a gate insulating layer and a first passivation layer provided with a first via, a second via and a third via, and a source and a drain. An entire orthographic projection of the active layer on the base substrate coincides with an orthographic projection of at least part of the buffer pattern on the base substrate. The orthographic projection of the buffer pattern on the base substrate is within a border of an orthographic projection of the light-shielding pattern on the base substrate, and its area is less than an area of the orthographic projection of the light-shielding pattern on the base substrate. One of the source and the drain is coupled to the active layer through the first via, and another one is coupled to the active layer through the second via and the light-shielding pattern through the third via.

Array substrate and method for manufacturing the same, display panel and display device

The present disclosure provides an organic thin film and a method for preparing the same, a display device, and an optical device, in which the method includes: providing a base substrate; forming an isomerization generating layer on the base substrate, the isomerization generating layer including a first region and a second region; adding a precursor solution on a surface of the isomerization generating layer away from the base substrate, and allowing surface energy of the second region to be greater than surface energy of the first region, so as to form the organic thin film from the precursor solution, the precursor solution being at least partially located in the second region.

Organic thin film having isomerization generating layer and method for preparing the same, display device and optical device

Controlling execution of application-specific hardware pipelines includes detecting, using computer hardware, a loop construct contained in a function within a design specified in a high-level programming language, extracting, using the computer hardware, the loop construct from the function into a newly generated function of the design, and generating, using the computer hardware, a state transition graph corresponding to the loop construct. The state transition graph can be pruned by relocating operations from the function entry state and the function exit state into the loop region. A circuit design defining, at least in part, a pipeline hardware architecture implementing the loop construct can be generated using the computer hardware based, at least in part, on the pruned state transition graph.

Application-specific hardware pipeline implemented in an integrated circuit

A stable aqueous dispersion of multi-stage polymeric particles comprising a polymer and an oligomer, and an aqueous freeze-thaw stable coating composition comprising the aqueous dispersion providing coatings made therefrom with acceptable scrub resistance.

Aqueous dispersion of multi-stage polymeric particles and process of making the same

The present application provides a method and device for obtaining a predicted image of a truncated portion, an imaging method and system, and a non-transitory computer-readable storage medium. The method for obtaining a predicted image of a truncated portion comprises preprocessing projection data to obtain, by reconstruction, an initial image of the truncated portion; and calibrating the initial image based on a trained learning network to obtain the predicted image of the truncated portion.

Method and device for obtaining predicted image of truncated portion

The invention relates to a KRAS mutant protein inhibitors of formula (I), a composition containing the inhibitors and the use thereof. 

Growing community of inventors

Beijing, China

Dan Liu