Cadence Design Systems, Inc.

Dan Leibovich

Alok Jain

Sandeep Pagey

Yaron Peri-Glass

Axel Siegfried Scherer

Frank Armbruster

John Paul Decker

Tal Yanai

F Erich Marschner

Paul Carzola

Arik Shmayovitsh

Jigar Patel

A method, system and non-transitory computer readable storage medium for coverage determination of DUT tests. The method may include obtaining via an input device a selection of a subset of interest of coverage reports included in one or a plurality of saved merged coverage reports. The method may further include using a processing unit, finding a saved merged coverage report of said one or a plurality of saved merged coverage reports that has the smallest number of unwanted coverage reports. The method may also include using the found saved merged coverage report to obtain a merged coverage report that corresponds to the subset and merging the merged coverage report with the newly gathered coverage reports into a new merged coverage report.

Method and system for coverage determination

A method and apparatus for producing a verification of digital circuits are provided. In an exemplary embodiment on the invention, a plurality of verification scopes of an integrated circuit design as defined as part of a verification plan. A plurality of verification runs are executed within two or more verification scopes defined by the verification plan. At least two verification runs are selected to merge verification results together. Like named scenarios are merged together for each verification scope to generate merged verification results that are then stored into a merge database. A verification report is generated for the integrated circuit design from the merged verification results. A merge point may be specified so like named subtrees and subgroups may be merged across different verification scopes of selected verification runs. The merge point may combine check and coverage results obtained during simulation with check and coverage results obtained during formal verification.

Verification plans to merging design verification metrics

A method for modeling power management in an integrated circuit (IC) includes: specifying a circuit design and a power architecture for the IC, the power architecture including a plurality of power domains for specifying power levels in different portions of the IC; determining a testbench for simulating the IC and a verification plan for evaluating simulation results; using the testbench to simulate variations in power levels of the power domains of the IC; and using the verification plan to evaluate the simulation results for the power domains of the IC.

Modeling power management for an integrated circuit

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Modiin, Israel

Dan Leibovich