Cray Research, Inc.

Supercomputer Systems Limited Partnership

Dan L Massopust

Edward C Priest

Frederick J Simmons

Steve S Chen

David A Hanson

Douglas C Paffel

Greg W Pautsch

Felix R Lesmerises

Michael H Rabska

Christopher J Sperry

Steven C Barber

Dennis F Girling

Ken Shintaku

Lisa Heid

Clock pulses from a master oscillator are distributed in a multiprocessor computer system so that they arrive at a large number of utilization points located in operating clusters of modules within extremely tight time tolerances of each other. The delays associated with each component, electrical or optical connection, cable or the like are determined by direct measurement or by using known standard characteristics. A time delay budget for each complete clock pulse path from the point of initial divergence from the master clock source to the final chip delivery point is logged and summed. Components capable of introducing predetermined amounts of time delay are incorporated in some or all clock pulse paths. These components are adjusted so as to balance out the differences determined from the clock path budgets. The clock paths are implemented in electrical components either alone or in combination with optical components, or in substantially all optical configurations. One arrangement for controlling optical skew includes an arrangement of optical elements physically displaceable in a coaxial direction relative to one another. Skew adjustment networks employ a unique composition of coarse and fine selectable delay arrays implemented either by electrical components, optical components, or a combination thereof.

Clock distribution apparatus and processes particularly useful in

The present invention includes methods and apparatus for creating a packaging architecture for a highly parallel multiprocessor system. The packaging architecture of the present invention can provide for distribution of power, cooling and interconnections at all levels of components in a highly parallel multiprocessor system, while maximizing the number of circuits per unit time within certain operational constraints of such a multiprocessor system.

Packaging architecture for a highly parallel multiprocessor system

A connector frame for use in the connection of electrical circuit assemblies having pins integrally connected therewith. The connector frame is a body of electrically non-conductive, thermally conductive material having one or more apertures bored through the body, said apertures being through-plated with an electrically-conductive material having a lower melting point than any of the surrounding materials. Said body also includes at least one separate aperture in which is disposed an electrically-conductive, heat-generating wire, said wire having the capacity to generate sufficient heat to melt the electrically-conductive material disposed in the apertures to form a strong electrical and mechanical bond between the pins of the electrical circuit assemblies.

High density disposable printed circuit inter-board connector

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Eau Claire, WI, United States of America

Dan L Massopust