Marvell Israel (misl) Ltd.

Dan Ilan

Guy Nakibly

Michael Weiner

Rabeeh Khoury

Itay Peled

Moshe Anschel

Eilon Argov

Adi Habusha

Noam Mizrahi

Eitan Joshua

Uri Dayan

Einat Ophir

Tawfik Bayouk

Eran Maor

Alon Rachmani

A packet processing system and method for processing data units are provided. A packet processing system includes a processor, first memory having a first latency, and second memory having a second latency that is higher than the first latency. A first portion of a queue for queuing data units utilized by the processor is disposed in the first memory, and a second portion of the queue is disposed in the second memory. A queue manager is configured to push new data units to the second portion of the queue and generate an indication linking a new data unit to an earlier-received data unit in the queue. The queue manager is configured to transfer one or more queued data units from the second portion of the queue to the first portion of the queue prior to popping the queued data unit from the queue, and to update the indication.

Device and method for packet processing with memories having different latencies

Embodiments include a network device comprising: at least one processing core; a packet processing module configured to perform a first set of packet processing operations at a first rate, to partially process data units that are received at the network device, the packet processing module being further configured to transmit ones of the data units to the at least one processing core, the at least one processing core being configured to perform a second set of processing operations at a second rate, wherein the second set of processing operations is different from the first set of processing operations; an interconnecting module configured to interconnect the packet processing module and the at least one processing core; and a rate limiter configured to selectively control a transmission rate at which the data units are transmitted by the packet processing module to the at least one processing core based on the second rate.

Method and apparatus for controlling a rate of transmitting data units to a processing core

A network device and method for packet processing are provided. A packet processing accelerator is configured to receive packets from a network and define for ones of the packets a data unit corresponding to the packet. The packet processing accelerator is configured to perform a first set of packet processing operations on the data unit. A central processing unit (CPU) is configured to perform a second set of packet processing operations on the data unit. A buffer is configured to pass data units from the packet processing accelerator to the CPU, and vice versa, where the buffer is configured to store data units in one or more lines of the buffer. Dummy data units fill a space in a buffer line that is not occupied by a data unit, and the dummy data units include an indication that the space occupied by the dummy data units is an empty space.

Network device and method for packet processing

Embodiments include a system on chip (SOC) comprising: a cache; a buffer manager configured to manage a plurality of buffer locations; and a processing core configured to issue a buffer allocation request to the buffer manager to request the buffer manager to allocate one or more buffer locations to the processing core, the buffer manager being further configured to, in response to receiving the buffer allocation request, allocate a first buffer location to the processing core by writing a first buffer pointer associated with the first buffer location to the cache, and the processing core being further configured to obtain the allocation of the first buffer location by reading the first buffer pointer from the cache.

Interfacing with a buffer manager via queues

Aspects of the disclosure provide an apparatus. The apparatus includes a display module configured to display an image frame on a screen based on pixel data of the image frame, a memory chip configured to include a frame buffer that stores pixel data of image frames to be displayed by the display module and an integrated circuit, such as a system on chip (SOC). The integrated circuit includes a memory controller coupled to the memory chip and configured to access the memory chip to fetch the pixel data from the frame buffer in response to data requests, and a display controller coupled to the display module. The display controller is configured to send data requests to the memory controller to fetch the pixel data from the frame buffer and transmit the pixel data to the display module when the apparatus is in a first mode, such as an active mode. Further, the display controller is configured to selectively drop a portion of the data requests to increase an idle time of the memory chip when the apparatus enters a second mode, such as an e-book mode, so that the memory chip enters a memory power saving mode when the apparatus is in the second mode.

Method and apparatus for refreshing a display

Some of the embodiments of the present disclosure provide a system-on-chip (SOC) that includes a plurality of processing cores; and a counter update module configured to atomically update a counter that is stored in a storage location, based on a counter update command received from a processing core of the plurality of processing cores; generate an ECC for the updated value of the counter; and write the updated value of the counter and the ECC to the storage location. Other embodiments are also described and claimed.

Counter update through atomic operation

Methods and systems for implementing video driving circuitry are disclosed. For example, in an embodiment, a system for driving a plurality of different types of video devices is disclosed. The system includes, for example, a System on a Chip (SoC) that itself includes a Liquid Crystal Display (LCD) controller circuit configured to generate digital video data, a first synchronization signal for controlling a first characteristic of the digital video data, and a second synchronization signal for controlling a second characteristic of the digital video data. The SoC further includes a delay circuit configured to variably delay the first synchronization signal and the second synchronization signal relative to the digital video data to generate a delayed first synchronization signal and a delayed second synchronization signal.

Display interface methods and systems

Aspects of the disclosure provide an integrated circuit. The integrated circuit includes a first memory, a memory controller, and a display controller coupled to a display module. The memory controller is selectively coupled to the first memory and to a second memory that has higher power consumption than the first memory. The second memory includes a frame buffer storing pixel data of images to be displayed on the display module. When the integrated circuit enters a power saving mode, the memory controller, while coupled to the first memory and the second memory, pre-fetches pixel data of an image from the second memory into the first memory at a first data rate. Further, when the integrated circuit is in the power saving mode, the display controller streams the pixel data from the first memory to the display module at a second data rate that is lower than the first data rate, and the second memory is configured into a memory power-saving mode after the pre-fetching until the second memory is accessed for additional pixel data.

Method and apparatus for refreshing display

Aspects of the disclosure provide a method for power mode switching. The method includes sending a pausing request to an application executed in an electronic system. The pausing request informs the application of an intent to switch the electronic system from an active mode to a power saving mode that causes the electronic system to pause executing the application. Then, the method includes determining that the application accepts the pausing request, and configuring the electronic system into the power saving mode, such that the application pauses at a pausing point determined in response to the pausing request.

Growing community of inventors

Herzellia, Israel

Dan Ilan