Tektronix, Inc.

General Signal Corporation

Transwitch Corporation

Microwave Logic

Dan H Wolaver

Daniel G Knierim

Daniel C Upp

Warren E Little

Donald J Delzer

Jeffrey A Kleck

J Howell Mitchell, Jr

Paul Chang

A jitter measurement method using a down-mixing or down-converting topology in a jitter measurement system preserves the jitter UI rather than the jitter seconds. An input serial data stream at a high baud is mixed with a stable local oscillator frequency that is close to that of the high baud. The difference between the high baud and the local oscillator frequency is passed by a filter as a lower rate serial stream. A clock recovery circuit recovers a lower rate clock from the lower rate serial stream, or an amplitude modulation removal stage converts the lower rate serial stream to a lower rate NRZ signal, or the lower rate serial signal is digitized. Jitter measurement is performed by a jitter measurement stage on the lower rate clock, the lower rate NRZ signal, or the digitized lower rate serial signal.

Jitter measurement using mixed down topology

A clock recovery system includes a source of a data signal having transitions, an injection-locked oscillator having a free-running frequency and generating a clock signal, and a free-running frequency adjustment circuit. The free running frequency adjustment circuit includes a transition density detector for detecting the density of the transitions in the data signal; a phase error detector for detecting the phase error between the clock signal and the data signal; and a correlator for adjusting the free-running frequency of the injection locked oscillator in response to the correlation between the detected transition density in the data signal and the phase error between the data signal and the local oscillator.

Free-running-frequency adjustment circuit for a clock recovery system

A clock recovery system includes a source of a data signal, and a free-running frequency adjustment circuit. The free-running frequency adjustment circuit includes an injection-locked oscillator having a free-running frequency and generating a clock signal and a phase locked loop, coupled in parallel with the injection locked oscillator, and generating a control signal adjusting the free running frequency of the injection locked oscillator.

Clock recovery system using wide-bandwidth injection locked oscillator with parallel phase-locked loop

A digital phase synthesizer includes a source of successive phase data signals. An interpolator generates successive edge placement data signals in response to each of the successive phase data signals. A phase modulator generates an output clock signal having edges placed at times determined by the successive edge placement data signals. Similarly, a digital phase analyzer includes a source of an serial binary input signal having edges. A phase demodulator generates successive data signals representing the location of each edge of the serial binary input signal. A decimator generates phase data signals at a lower rate than the edges of the serial binary input signal.

Digital phase analyzer and synthesizer

A phase modulator circuit and method for generating an output signal having individually positionable edges is described. The phase modulator includes a programmable pulse generator, such as an interval counter, a delay, or a ring oscillator for producing the output signal, and a control value source, such as a memory, for delivering a sequence of control values to the generator. The control values determine the time between successive output pulses. A programmable interval counter includes a free running counter, the output of which is compared to a control value, preferably stored as a modulo data value, to generate an output pulse. A first programmable delay circuit includes a ring oscillator having plural delay lines for fine control of edge positioning. To fully synchronize the delay circuit to a coarse control interval counter, the clock input to the interval counter can be provided by the ring oscillator. A second programmable delay circuit uses interpolation to achieve finer resolution between time positions. The interval counter can be combined with the first and second delay circuits to achieve coarse, fine, and very fine resolution, respectively in a phase modulator.

Phase modulator having individually placed edges

An SRTS clock recovery apparatus and method are provided. The apparatus broadly includes a controllable destination node clock generator such as a digitally controllable oscillator, a block for generating a local RTS-related value from the destination node clock and the system reference clock, and a comparator which compares the incoming RTS-related value to the local RTS related value to provide a feedback error or control signal which is used to adjust the controllable clock generator. If desired, a filter which filters the error signal can be provided in the loop. With the feedback loop as provided, when the destination node clock is faster than the source clock, the error signal will cause the destination node clock to slow, and vice versa.

Closed loop clock recovery for synchronous residual time stamp

A phase modulator circuit and method for generating an output signal having individually positionable edges is described. The phase modulator includes a programmable pulse generator, such as an interval counter, or a delay for producing the output signal, and a control value source, such as a memory, for delivering a sequence of control values to the generator. The control values determine the time between successive output pulses.

The phase range of a phase detector is extended while maintaining its modulation bandwidth and linearity. The range is widened by dividing down the frequencies to be compared. Clocked delay lines create sequentially delayed multiple-phase signals which are applied to a plurality of component phase detectors. The outputs of each of the component phase detectors are summed to restore the frequency of the original clock signals to the output components. This technique is especially useful in high-speed phase detectors.

Wide-range, wide-bandwidth, high-speed phase detector

A digital clock dejitter circuit has a RAM for receiving an incoming gapped signal, a digital, fractional RAM fullness gauge for tracking the average input and output rates to and from the RAM and for generating therefrom a control indication, and a controllable digital frequency generator for receiving a fast clock signal and the control indication, and for providing therefrom a substantially jitter-free clock signal at the same nominal rate as the incoming gapped signal. The RAM fullness gauge has write and read counters which track the movement of data into and out of the RAM, and a subtractor for taking the difference of the counters to obtain the integer value of the RAM depth. The controllable digital frequency generator has an adder, a register, and a fast clock counter (FCC) which provides the fullness gauge with a fractional digital indication of the RAM depth. The adder has a carry output fed to the FCC to control whether the FCC divides by x or x+1, and a remainder output fed to the register and then fed back as an input to the adder. The adder also receives the control indication from the fullness gauge as an input. FCC inputs include the fast clock, and the carry output of the adder. The FCC outputs are a read signal for causing a byte to be read from the RAM at the end of a count cycle, and the fast clock count used for fractional fullness.

Digital clock dejitter circuits for regenerating clock signals with

A linear three-state phase detector capable of accurately responding to simultaneous input signals has its linear range extended by uniquely sensing cycle slip and stepping a binary up-down counter. The cycle slip detector is capable of handling simultaneous inputs by determining that a resulting change of the three-state phase detector output occurs after a predetermined time after an input signal.

Extended range phase detector

A phase locked loop circuit for high frequency digital electronic signals is provided which includes a loop filter having a substantially infinite bandwidth and wherein the sum of the frequency comparator and phase comparator output signals is actively integrated by an operational amplifier and summed with a flat, passively attenuated signal from the phase comparator. The PLL circuit includes a phase comparator having a full adder employing current mode logic so as to reduce parasitic capacitances and stray voltages, a frequency comparator having an additional, final flip-flop means out of the final combinatorial logic so as to retain the polarity of the final waveform transition, and an inhibiting circuit to disable the output of the final flip-flop of the frequency comparator when phase lock is attained by adding a complementary signal thereto.

High speed phase locked loop filter circuit

A wide range, variable rate clock recovery circuit for NRZ data is provided having a PLL and a frequency synthesizer which share control of a common VCO in single loop realization. Narrow PLL bandwidths and short acquisition time may be achieved employing the frequency synthesizer to initially control the VCO to produce an estimate of the data frequency which is accurate to within the bandwidth of the PLL. Once this VCO frequency is attained, the PLL disables the frequency synthesizer control of the VCO and provides fine tuning control of the VCO output frequency itself. Single loop realization is achieved with a wide range VCO which includes a narrow range VCO, a frequency divider, and an auto-ranging circuit.

Wide range clock recovery circuit

A PLL frequency detector or comparator is provided having an up-down counter, responsive to beat signals produced by the input periodic waveforms of the VCO reference signals and the input data signals, to produce top and bottom output signals which enable multivibrators connected to each of the input signal lines to transmit overflow and underflow output pulses, whose sum is proportional to the difference in frequency of the input signals up to a predetermined maximum level, as control signals for the PLL loop filter. The up-down counter may include three or more states with buffer states which prevent generation of overflow or underflow output signals when the PLL is within a predetermined region of phase-lock and the sign of the beat signal oscillates. The up-down counter may also be employed simultaneously as a phase detector or comparator, wherein the top and bottom output signals are combined so as to produce control signals for the PLL loop filter when the overflow and underflow output signals are not generated.

Fast acquisition phase-lock loop

A phase locked loop circuitry for high frequency digital electronic signals is provided which includes a loop filter having a substantially infinite bandwidth and wherein the sum of the frquency comparator and phase comparator output signals is actively integrated by an operational amplifier and summed with a flat, passively attenuated signal from the phase comparator. The PLL circuit includes a phase comparator having a full adder employing current mode logic so as to reduce parasitic capacitances and stray voltages, a frequency comparator having an additional, final flip-flop means out of the final combinatorial logic so as to retain the polarity of the final waveform transition, and an inhibiting circuit to disable the output of the final flip-flop of the frequency comparator when phase lock is attained by adding a complementary signal thereto.

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West Brookfield, MA, United States of America

Dan H Wolaver