International Business Machines Corporation

Amdahl Corporation

Dan F Greiner

Timothy John Slegel

Christian Jacobi

Damian Leo Osisek

Lisa Cranton Heller

Charles W Gainey, Jr

Donald W Schmidt

Fadi Y Busaba

Michael K Gschwind

Chung-Lung K Shum

Marcel Mitran

Mark S Farrell

Gustav E Sittmann, Iii

Erwin F Pfeffer

Jonathan D Bradbury

Valentina Salapura

Maged M Michael

Thomas Anthony Gregg

David F Craddock

Jeffrey Paul Kubala

John Robert Ehrman

Anthony Saporito

Charles Franklin Webb

Eric M Schwarz

Tamas Visegrady

Beth A Glendening

Bernd Nerz

Harold Wade Cain, Iii

Volodymyr Paprotski

Robert R Rogers

Timothy J Siegel

Joachim Von Buttlar

Donald William Schmidt

Charles Gainey

Anthony F Coneski

John Robert Dravnieks

Fadi Yusuf Busaba

Jonathan David Bradbury

Peter Grimm Sutton

Elpida Tzortzatos

Peter Kenneth Szwed

Eric N Lais

Peter Jeremy Relson

James H Mulder

Scott B Tuttle

Christian Zoellin

Michel H T Hack

Younes Manton

Eberhard Engler

Damian Osisek

Leslie W Wyman

Jaya Srikrishnan

Randall W Philley

Robert W StJohn

Mike S Fulton

Eric Norman Lais

Reinhard Theodor Buendgen

Ronald Morton Smith, Sr

David Arlen Elko

David Harold Surman

Ute Gaertner

Aaron Tsai

Mark Anthony Check

Richard K Errickson

Frank Siegfried Lehnert

Steven N Goss

Ugochukwu Charles Njoku

Aditya Nitin Puranik

Carol B Hernandez

Robert M Abrams

Kai Chiu Wong

Mike Stephen Fulton

Joran S C Siu

Charles E Webb

Cynthia Sittmann, Legal Representative

Frank Lehnert

Iii Sittmann

Jr Gainey

Chung-Lung Shum

Randall William Philley

Anthony Coneski

Charles (deceased) Gainey

A clock comparator sign control is used in a compare operation. A clock comparator sign control that determines whether unsigned arithmetic or signed arithmetic is to be used in a comparing operation is obtained. The clock comparator sign control is then used in a comparison of a value of a clock comparator and at least a portion of a value of a time-of-day clock to determine whether a selected action is to be recognized.

Clock comparator sign control

In a processor supporting execution of a plurality of functions of an instruction, an instruction blocking value is set for blocking one or more of the plurality of functions, such that an attempt to execute one of the blocked functions, will result in a program exception and the instruction will not execute, however the same instruction will be able to execute any of the functions that are not blocked functions.

Function virtualization facility for blocking instruction function of a multi-function instruction of a virtual processor

Selected installed function of a multi-function instruction is hidden such that even though a processor is capable of performing the hidden installed function, the availability of the hidden function is hidden such that responsive to the multi-function instruction querying the availability of functions, only functions not hidden are reported as installed.

Function virtualization facility for function query of a processor

A system and method of executing a plurality of threads, including a first thread and a set of remaining threads, on a computer processor core. The system and method includes determining that a start interpretive execution exit condition exists; determining that the computer processor core is within a grace period; and entering by the first thread a start interpretive execution exit sync loop without signaling to any of the set of remaining threads. In turn, the first thread remains in the start interpretive execution exit sync loop until the grace period expires or each of the remaining threads enters a corresponding start interpretive execution exit sync loop.

Efficiency for coordinated start interpretive execution exit for a multithreaded processor

A TRANSACTION BEGIN instruction and a TRANSACTION END instruction are provided. The TRANSACTION BEGIN instruction causes either a constrained or nonconstrained transaction to be initiated, depending on a field of the instruction. The TRANSACTION END instruction ends the transaction started by the TRANSACTION BEGIN instruction.

Transaction begin/end instructions

An enhanced dynamic address translation facility product is created such that, in one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. Dynamic address translation of the virtual address proceeds. In response to a translation interruption having occurred during dynamic address translation, bits are stored in a translation exception qualifier (TXQ) field to indicate that the exception was either a host DAT exception having occurred while running a host program or a host DAT exception having occurred while running a guest program. The TXQ is further capable of indicating that the exception was associated with a host virtual address derived from a guest page frame real address or a guest segment frame absolute address. The TXQ is further capable of indicating that a larger or smaller host frame size is preferred to back a guest frame.

Creating a dynamic address translation with translation exception qualifiers

A guarded storage facility sets up a boundary indicating a range of addresses to be guarded or protected. When a program attempts to access an address in a guarded section defined by the boundary, a guarded storage event occurs. Use of this facility facilitates performance of certain tasks within a computing environment, including storage reclamation.

Identifying processor attributes based on detecting a guarded storage event

What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. Based on the origin address, a segment table entry is obtained which contains a format control field and an access validity field. If the format control and access validity are enabled, the segment table entry further contains an access control and fetch protection fields, and a segment-frame absolute address. Store operations to the block of data are permitted only if the access control field matches a program access key provided by either a Program Status Word or an operand of a program instruction being executed. Fetch operations from the desired block of data are permitted only if the program access key associated with the virtual address is equal to the segment access control field.

Dynamic address translation with access control in an emulator environment

A facility and cache machine instruction of a computer architecture for specifying a target cache cache-level and a target cache attribute of interest for obtaining a cache attribute of one or more target caches. The requested cache attribute of the target cache(s) is saved in a register.

Extract target cache attribute facility and instruction therefor

A Conditional Transaction End (CTEND) instruction is provided that allows a program executing in a nonconstrained transactional execution mode to inspect a storage location that is modified by either another central processing unit or the Input/Output subsystem. Based on the inspected data, transactional execution may be ended or aborted, or the decision to end/abort may be delayed, e.g., until a predefined event occurs. For instance, when the instruction executes, the processor is in a nonconstrained transaction execution mode, and the transaction nesting depth is one at the beginning of the instruction, a second operand of the instruction is inspected, and based on the inspected data, transaction execution may be ended or aborted, or the decision to end/abort may be delayed, e.g., until a predefined event occurs, such as the value of the second operand becomes a prespecified value or a time interval is exceeded.

Conditional transaction end instruction

Guarded storage event handling during transactional execution

An instruction for parsing a buffer to be utilized within a data processing system including: an operation code field, the operation code field identifies the instruction; a control field, the control field controls operation of the instruction; and one or more general registers, wherein a first general register stores an argument address, a second general register stores a function code, a third general register stores length of an argument-character buffer, and the fourth of which contains the address of the function-code data structure.

Parsing-enhancement facility

A system and method of implementing a wait state for a plurality of threads executing on a computer processor core of the processor. The processor is configured to execute instruction streams by the plurality of threads, wherein the plurality of threads includes a first thread and a set of remaining threads and determine that the first thread has entered a first wait state loop. The processor is also configured to determine that any of the set of remaining threads has not entered a corresponding wait state loop and remain by the first thread in the first wait state loop until each of the set of remaining threads has entered the corresponding wait state loop.

Growing community of inventors

San Jose, CA, United States of America

Dan F Greiner