Barcelona Design, Inc.

Totic Technology Inc.

Dan Bui

Choshu Ito

Sunderarajan S Mohan

Eric Soenen

Paul B Morton

A method and system for designing an integrated circuit layout are disclosed. In one embodiment, the method includes generating a stem cell library with stem cell layouts, wherein each stem cell layout includes an analog core area where a device element resides, and abutment boundaries on left, right, top, and bottom sides of the analog core area. The method also includes mapping device elements in a schematic netlist to the stem cell layouts in the stem cell library. In addition, the method includes placing and routing the mapped device elements to optimize a layout for the schematic netlist.

Method and apparatus for performing layout designs using stem cells

A power distribution circuit built with wiring layers that reside above an analog circuit is described. The power distribution circuit comprises one or more capacitive structures that reside above the analog circuit. At least one of the one or more capacitive structures has electrodes that provide supply and/or reference voltages and their corresponding currents to said analog circuit. A machine readable medium is described to perform a method in order to design the power distribution circuit. The method includes: assigning a specific supply or reference voltage to each of the electrodes; and, determining wiring dimensions for each of the electrodes. The wiring dimensions for the electrodes of at least one of the capacitive structures is are based at least in part on IR drop concerns.

Analog circuit power distribution circuits and design methodologies for producing same

A capacitive structure is described that comprises a first node and a second node. The first node comprises a first pair of vertically aligned strips that are electrically connected with one or more vias and a second pair of vertically aligned strips that are electrically connected with one or more vias. The higher strips of both of the pairs are at a same metal level and the lower strips of both of the pairs are at a same lower metal level. The second node comprises, at the metal level, a first metal structure having a pair of windows. A first of the windows surround and are isolated from a first of the higher strips. A second of the windows surround and are isolated from a second of the higher strips. The second node also comprises, at the lower metal level, a second metal structure having a pair of windows. A first of the windows surround and are isolated from a first of the lower strips. A second of the windows surround and are isolated from a second of the lower strips. The first and second metal structures are electrically connected with one or more vias.

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Sunnyvale, CA, United States of America

Dan Bui