National Semiconductor Corporation

Dan Biran

Ohad Falik

Gideon Intrater

Chaim Bendelac

Rami Saban

Jonathan Levy

Zeev Bikowsky

Gadi Erlich

Aharon Ostrer

Gigi Baror

Moti Beck

Benny Konstantin

Jonanthan Levy

Elliot Cohen

Yair Hadas

Alon Shackam

Boaz Shahar

A processor core for provides a linear extension of addressable memory space of a microprocessor with minimal additional hardware and software complexity. A N+x bit pointer register (e.g. program counter) holds an N+x bit instruction address. The N+x bit instruction address provides to an execution unit a pointer to an instruction in the memory to be processed by the execution unit. An encoder encodes the N+x bit address into an N bit encoding of the N+x bit address. The processor core can thereby address 2.sup.x times more memory locations than 2.sup.N. Two other registers each hold a portion of an data address (i.e. a pointer to a datum in memory to be operated on). An address former concatenates the portions of the address in the two registers to form the data address. Therefore, the address is formed from portions of the data address stored in multiple registers without performing any arithmetic on the portions.

Processor core which provides a linear extension of an addressable

A method and apparatus for prechecking (probing) the validity of an access request for writing result data to an external system prior to executing the instruction that generates the result is provided. This allows instruction execution to continue uninterrupted in the event that the write is allowed. The microprocessor's Address Unit issues a 'probe' request to the Memory Management Unit (MMU) via an internal bus while saving the instruction's virtual address in a virtual address buffer local to the Address Unit. The MMU checks the validity of the 'probe' request without converting the virtual address to a physical address and issues an access grant signal which is saved by the microprocessor's Execution Unit for subsequent use. The Execution Unit processes the data in parallel to the MMU checking the validity of the probe request. If the virtual address associated with the probe request resulted in an access grant signal, then the Execution Unit issues a write request while the virtual address previously stored in the Address Unit is sent to the MMU for translation to a physical address. Both the write data and the physical address are stored in a buffer in the microprocessor's Bus Interface Unit (BIU) for subsequent transfer to an external system. The data is then written to the external system at the physical address provided by the BIU.

Method of prechecking the validity of a write access request

A method and apparatus for observing the contents on internal memory-mapped registers of controllers and co-processors which have been integrated on-chip with a central processing unit ('CPU'). The CPU asserts a first signal when access to internal memory is requested and deactivates a second signal which would normally allow simultaneous access to both internal and external memory locations. In this way, the contents of internal memory may be observed in real time.

Method and apparatus for observing internal memory-mapped registers

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Raanana, Israel

Dan Biran