Intel Corporation

Dan Biederman

Michael Orr

Gabriel Arrobo Vidal

Kenneth G Keels

Jose Niell

Patrick Fleming

Robert W Cone

Matthew James Webb

Chih-Jen Chang

Brad Burres

Haichuan Tan

Pradeep Sakhamoori

Pat Wang

Systems and techniques for microservice latency reduction are described herein. A request may be received for execution of a microservice. An execution time may be calculated for the microservice. The execution time may be an estimation of time to complete execution of the microservice. A service level objective (SLO) may be identified. A processing unit of a computing node may be identified for execution of the microservice based on the precise execution time and the SLO. The microservice may be transmitted to the processing unit for instantiation.

Microservice latency reduction

Technologies for an accelerator interface over Ethernet are disclosed. In the illustrative embodiment, a network interface controller of a compute device may receive a data packet. If the network interface controller determines that the data packet should be pre-processed (e.g., decrypted) with a remote accelerator device, the network interface controller may encapsulate the data packet in an encapsulating network packet and send the encapsulating network packet to a remote accelerator device on a remote compute device. The remote accelerator device may pre-process the data packet (e.g., decrypt the data packet) and send it back to the network interface controller. The network interface controller may then send the pre-processed packet to a processor of the compute device.

Technologies for accelerator interface

Various systems and methods for implementing a flexible packet processing mechanism are provided herein. A network interface device for implementing flexible packet processing includes a packet parser to: receive a packet; and determine from analyzing the packet, a corresponding processing element that is used to process the packet; and a coordinator circuit to: determine whether the processing element is active in a computing unit; load the processing element when it is not active; and forward the packet to the processing element.

Flexible packet processing

Particular embodiments described herein provide for an electronic device that includes at least one processor operating at eight hundred (800) megahertz and can be configured to receive a data stream, parse packets in the data stream, and process at least two (2) full packets from the data stream in a single clock cycle. In an example, the data stream is at least a two hundred (200) gigabit Ethernet data stream and a bus width is at least thirty-two (32) bytes.

Scalable packet processing

Various systems and methods for implementing intelligent packet aggregation are provided herein. A network interface device for implementing intelligent packet aggregation including a packet parser to receive a plurality of packets and route each packet of the plurality of packets to a queue of a plurality of queues, the packets divided among the queues based on the packets' characteristics; and a coordinator circuit to: interface with a processing element to determine a current operational state of the processing element; select a queue from the plurality of queues based on the current operational state of the processing element; and forward a number of packets from the selected queue to the processing element.

Growing community of inventors

Saratoga, CA, United States of America

Dan Biederman