International Business Machines Corporation

Damon W Finney

James T Brady

Michael Howard Hartung

Michael Anthony Ko

David R Nowlen

Jaishankar Moothedath Menon

Donald J Lang

Noah R Mendelsohn

Narasimhareddy L Annapareddy

Michael James Rayfield

Michael T Benhase

Michael O Jenkins

Richard Francis Freitas

George B Marenin

Andrew Dale Walls

Adalberto Guillermo Yanes

Richard L Schober, Jr

Marc A Schaub

Mark C Johnson

Paul W Hunter

Peter Paul Urbisci

David N Mora

David A Plomgren

Calvin Kuo-Lee Tang

Shin-Yuan Tzou

Wen-Jei Ho

Lawrence Marcel Brown

Albert C Kuo

Jai M Menon

Paul S Serris

Larry B Kessler

Song C Liang

Narasimha Lakshmi Annapareddy

Ashwin S Subramanian

Embodiments relate to an image signal processor that includes an image processing circuit, a buffer, and a rate limiter circuit. The image processing circuit perform operations associated with image signal processing. The buffer stores the image data provided by the system memory. The buffer includes a shared that is dynamically allocated among the image processing circuits. The rate limiter circuit arbitrates allocation of the shared section. The arbitration process includes allocating data credits for the shared section to an image processing circuit. The rate limiter circuit determines a first number of blocks in the shared section that are allocated for pending requests and a second number of blocks that include data pending to be consumed by the image processing circuit. If the total allocated blocks occupied by the image processing circuit exceed a throttling threshold, the image processing circuit will be throttled by an exponential factor.

Shared dynamic buffer in image signal processor

Conflicts are resolved between competing nodes in a multi-node communications network. After a first node in the network requests an initiation of communications with a target node, the requesting node may simply initiate the requested communications with the target node if the target node is not busy. If the first node determines that the target node is busy, it proceeds to resolve the conflict. Namely, the first node repeats the process of waiting for a first delay then requesting initiation of communications with the target node. After each unsuccessful attempt, the first delay is successively increased. As an example, the delay may be increased exponentially, with a controlled randomness added. After a or more queued messages to other nodes. Following this, the first node performs another sequence to initiate communications with the target node, successively increasing the delay between unsuccessful attempts, as before. After a predetermined number of unsuccessful passes through the foregoing routine, the first node proceeds to take appropriate action, such as initiating an error recovery routine, sending the message via different hardware components, or issuing an error message.

Conflict resolution in multi-node communication network

A procedure controls execution of priority ordered tasks in a multi-nodel data processing system. The data processing system includes a node with a software-controlled processor and a hardware-configured queue-controller. The queue-controller includes a plurality of priority-ordered queues, each queue listing tasks having an assigned priority equal to a priority order assigned to the queue. The queue-controller responds to a processor generated order to queue a first task for execution, by performing a method which includes the steps of: listing said first task on a first queue having an assigned priority that is equal to a priority of said first task; if a second task is listed on a queue having a higher assigned priority, attempting execution of the second task before execution of the first task; if no tasks are listed on a queue having a higher assigned priority than said first queue, attempting execution of a first listed task in the first queue means; and upon completion of execution of the task or a stalling of execution of the task, attempting execution of a further task on the first queue only if another order has not been issued to place a task on a queue having a higher assigned priority. The method further handles chained subtasks by attempting execution of each subtask of a task in response to the processor generated order; and if execution of any subtask does not complete, attempting execution of another task in lieu of a subtask chained to the subtask that did not complete.

System and method for queuing of tasks in a multiprocessing system

A method enables a host processor, which employs variable length (VL) records, to transparently communicate with disk storage which employs fixed length (FL) sectors for storage of the VL records. The method comprises the steps of: a) deriving a first control data structure for an update VL record, the first control data structure including information describing segments of the update VL record; b) determining an FL sector wherein an old VL record commences that corresponds to the update VL record; c) if the old VL record commences at other than a sector break of the FL sector, deriving a second control data structure for a portion of a prior VL record that immediately precedes the old VL record and a third control data structure for the old VL record; d) substituting in the third control data structure, information regarding update segments of the update VL record from the first control data structure; and recording in the FL sector determined in c), data indicated by the second control data structure and at least a portion of the update VL record, through use of the third control structure as altered in d).

Method for extraction of a variable length record from fixed length

A method enables a host processor, which employs variable length (VL) records, to communicate with disk storage which employs fixed length (FL) sectors for storage of the VL records. The method comprises the steps of: a) deriving a first control data structure for an update VL record, the first control data structure including information describing segments of the update VL record; b) determining a disk track that includes a FL sector wherein am old VL record commences that corresponds to the update VL record; c) reading each FL sector in the disk track and creating a control data structure which includes information describing each VL record stored in the disk track; d) substituting in a control data structure for the old VL record that corresponds to the update VL record, information regarding update data from the first control data structure; e) recording in the disk track, data indicated by each control data structure determined in steps c) and d); and f) if the old VL record ends at other than a sector break of a FL sector, reblocking VL records into FL sectors which are recorded thereafter on the disk track. The invention also enables a read action to be accomplished in one rotation of a disk even though it commences at a FL sector that is not at the beginning of a VL record to be accessed.

A common macro interface between chips that have design features in common and communicate with each other. The common macro interface (CMI) uses VHDL (VHSIC Hardware Description Language) which is the industry standard hardware design language. A common protocol is provided to resolve communication problems and comprises four signals: request; acknowledge request; data acknowledge, and read/write. A freeway system within the interfaces facilitates parallel and pipelining processes and an arbiter (also called a scheduler) is placed in front of every slave resource to control the traffic independently and to avoid traffic collisions from locking the freeway. The freeway is unique for each integrated circuit. Accordingly, macros may be moved from chip to chip without requiring complete system modifications and the effort involved in designing macros common to several chips may be shared.

Method and apparatus for parallel and pipelining transference of data

An apparatus for dynamically allocating memory includes a processor, a free buffer pool memory and a control memory which stores control block data structures. The control block data structures enable a segmentation of the free buffer pool memory into a series of free buffer pools, each free buffer pool comprising plural identical size buffers, each succeeding free buffer pool including a larger buffer size than a preceding free buffer pool. A selection size parameter for a given free buffer pool is a value that is larger than the buffer size comprising the given free buffer pool, but less than a next larger buffer size in the next of the series of free buffer pools. A memory allocation procedure responds to a request from an executing procedure for allocation of buffer space by: (i) allocating a buffer from a free buffer pool memory whose associated selection size parameter is a next larger value than the buffer space that was requested; (ii) determining a difference between the allocated buffer size and the requested buffer space to find an unfulfilled amount of the requested buffer space; (iii) allocating a buffer from a free buffer pool memory whose selection size parameter is a next larger value, among selection size parameters, than the unfulfilled amount; and (iv) repeating ii and iii until the memory allocation procedure determines that there is no unfulfilled amount of the requested buffer space. The apparatus further includes 'quickcell' memory which is allocated without use of control block data structures.

Dynamic memory allocation that enalbes efficient use of buffer pool

A multi-nodal data processing system includes a plurality of processing nodes, each node connected to plural other nodes by bidirectional data links. Each node comprises receivers for receiving messages on bidirectional data links and transmitters for transmitting messages on bidirectional data links. Each node records child nodes to which a message was transmitted and is further adapted to transmit a lock-up message received from a child node to a parent node, the lock-up message indicating a successful establishment of a message signal path to a destination node. Each node further is adapted to transmit a link cancel signal to another node to close the link in the event of an unsuccessful message transfer attempt over the link. Each node inhibits transmission of a lock-up signal to a parent node until link cancel signals have been received from all child nodes (other than a node from which a lock-up signal was received). A source node (where a message originates) continues transmission of its message, even before a lock-up signal has been received. The destination node which originates the lock-up message terminates a bidirectional data link by an end-of-session signal when it has received an entire message.

Method and system for message status reporting in a multi-node network

A test link protocol which continuously monitors each link in a network to ensure that the link is correctly transmitting data. Each switch, or torus has at least one of two functional components: Send Test and Receive Test. The Send Test component monitors control codes at a torus link output. The Receive Test component monitors control codes at a torus link input. After a predetermined interval, the Send Test component makes a request to send a test.sub.-- link control code. The torus sends the test.sub.-- link code to the neighboring torus, where it is removed from the data stream and sent to that torus' Receive Test. The Receive Test then generates a response message and makes a request to send that message back to the originating torus. After receiving the message, the Send Test analyzes the message to determine whether the network link is working correctly. An error is also declared if the Send Test does not receive a reply within a predetermined interval.

Method and apparatus for testing links between network switches

A system that enables pipelining of data to and from a memory includes multiple control block data structures which indicate amounts of data stored in the memory. An input port device receives and stores in memory, data segments of a received data message and only updates status information in the software control blocks when determined quantities of the data segments are stored. An output port is responsive to a request for transmission of a portion of the received data and to a signal from the input port that at least a first control count of data segments of the received data are present in memory. The output port then outputs the stored data segments from memory but discontinues the action if, before the required portion of the received data is outputted, software control blocks indicate that no further stored data segments are available for outputting. The input port then updates the software control blocks when newly arrived and stored data segments reach a second control count value, the updating occurring irrespective of whether the determined quantity of the received data has been stored in memory.

Method and apparatus for enabling pipelining of buffered data

A data processing system includes one or more processors connected to a common bus, one or more I/O controllers connected to the common bus and to one or more storage subsystems and one or more storage subsystems for storing data for use in the data processing system. One or more master controllers are included in each I/O controller for communicating with a memory controller referred to as a slave which controls data flow to and from a memory subsystem. The data bus between the I/O masters and the memory controller is a multi-drop operating synchronously on a two-by-two byte parallel interface.

System for controlling responses to requests over a data bus between a

A distributed data processing system includes a plurality of nodes interconnected by bidirectional communication links. Each node includes a control message line for handling of control messages and a control memory for storing the control messages. Each node further includes data message line for handling of data messages and a data memory for storing the data messages. A processor in the node causes the data message line to queue and dispatch data messages from the data memory and the control message line to queue and dispatch control messages from the control memory. Each node includes N bidirectional communication links enabling the node to have at least twice as much input/output bandwidth as the control message line and data message line, combined. An input/output switch includes a routing processor and is coupled between the N bidirectional communication links, the data message line and control message line. The input/output switch dispatches either a control message or a data message over at least one of the bidirectional communication links in accordance with an output from the routing control processor, thereby enabling each communication link to carry either data or control messages. If a communication link is busy with either a control or a data message, the routing control processor increments to another communication link to enable dispatch of a queued message.

Multi-node network with internode switching performed within processor

A multi-nodal computing system is connected by a communication network. A first node of the multi-nodal system includes apparatus for transmitting an information transfer request to a second node, the request including identification data that the second node can use to access the selected information. The second node includes memory for storing the requested information and a message output control structure. A processor is responsive to received identification data from the first node to access selected information that is defined by the data. The processor is further responsive to the information transfer request to insert the identification data received from the first node directly into a message output control structure. The processor then initiates an output operation by employing the identification data in the message output control data structure to access the identified information and to communicate the information to the first node. In such manner, no processor interrupt is required (with software intervention) to enable the requested information to be transferred, as pointers to that information are already included in the message output control structure, with the output mechanism in the second node employing that output control structure to access and transmit the requested information.

Expedited message transfer in a multi-nodal data processing system

A multi-node data processing system implements a method that assures that plural messages are enabled 'fair' access to a data stream. Each node includes apparatus for controlling message transmissions and/or receptions from another node over a communication network. The method comprises the steps of: transmitting a routing message from a first destination node to a source node, the routing message signalling a readiness of the destination node to receive a data message; transmitting a first data message to the first destination node from the source node in response to the ready message; transmitting a conditional disconnect message from the first destination node to the source node upon receipt of a predetermined amount (i.e. a 'slice') of the first data message. The source node responds to the conditional disconnect message by either (1) disconnecting from the first destination node, and commencing transmission of a slice of a second data message to a second destination node if during transmission of the slice of the first data message, the source node has received a ready message from the second destination node; or (2) continuing transmission of the data message to the first destination node until message end or, following the procedure in (1) if a new ready message is received by the source node from a further destination node, whichever occurs first.

Method and apparatus for assuring that multiple messages in a multi-node

A data processing system includes a software interrupt handler which controls performance of interrupt actions. The system further includes plural subsystems, each subsystem manifesting an interrupt request upon occurrence of an associated event. Hardware is provided which responds to an interrupt request by issuing an order to construct an interrupt status block (ISB) control data structure with a determined priority ranking. A controller is responsive to the issued order and constructs the ISB data structure. The ISB at least includes a pointer value indicating a next ISB having a same priority ranking, interrupt data identifying an interrupt procedure to be used by the software interrupt handler and information indicating a source of the interrupt request. The controller arranges the ISB in a queue of ISB's having a same determined priority and signals the software interrupt handler to commence performance of an interrupt action only if the order issued by the hardware requires an immediate interrupt. In such case, the software interrupt handler responds by reading contents of the ISB and performing operations in accordance with that data. Otherwise, normal processing resumes. Under normal circumstances, the controller, in executing an interrupt, is not required to inquire of the subsystem which manifested the interrupt request.

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Damon W Finney