Texas Instruments Corporation

Damien Thomas Gilmore

Mark Francis Arendt

Binghua Hu

Jonathan Philip Davis

Eugene C Davis

Shariq Arshad

Bill Alan Wofford

Khanh Quang Le

Robert Ray Spangler

Azghar H Khazi-Syed

Nicholas Andrew Kusek

Kaneez Eshaher Banu

Michael Glenn Williams

Ingu Song

Jonathan Roy Garrett

Kenneth Ryan Thomas

Mindricelu P Eugen

Sarah Elizabeth Bradshaw

Described examples include a method having steps of forming an isolation pad oxide layer on a substrate and forming and patterning a silicon nitride layer on the isolation pad oxide layer. The method also has steps of oxidizing portions of the substrate not covered by the silicon nitride layer to form a LOCOS layer and oxidizing the silicon nitride layer in an oxidizing ambient containing a chlorine source to form a silicon dioxide layer.

Gate and locos dielectrics grown using locos processing

A semiconductor device including a first dielectric layer and a second dielectric layer is formed by forming an inhibitor layer over a semiconductor material. The inhibitor layer includes at least silicon and nitrogen. The semiconductor material is heated in an oxygen-containing ambient which oxidizes the inhibitor layer and forms the first dielectric layer which includes the oxidized inhibitor layer, and oxidizes the semiconductor material to form the second dielectric layer. The second dielectric layer is thicker than, the first dielectric layer. The first dielectric layer and the second dielectric layer each include at least 90 weight percent silicon dioxide and less than 1 weight percent nitrogen. The first dielectric layer and the second dielectric layer may be used to form gate dielectric layers for a first MOS transistor and a second MOS transistor that operates at a higher voltage than the first MOS transistor.

Dual gate dielectric layers grown with an inhibitor layer

A microelectronic device with a trench structure is formed by forming a trench in a substrate, forming a seed layer in the trench, the seed layer including an amorphous dielectric material; and forming semi-amorphous polysilicon on the amorphous dielectric material. The semi-amorphous polysilicon has amorphous silicon regions separated by polycrystalline silicon. Subsequent thermal processes used in fabrication of the microelectronic device may convert the semi-amorphous polysilicon in the trench to a polysilicon core. In one aspect, the seed layer may be formed on sidewalls of the trench, contacting the substrate. In another aspect, a polysilicon outer layer may be formed in the trench before forming the seed layer, and the seed layer may be formed on the polysilicon layer.

Method of reducing voids and seams in trench structures by forming semi-amorphous polysilicon

A method of process control for a batch process includes pre-measuring a monitor lot to obtain pre-metrology data regarding at least a first process parameter. There are no product units included with the monitor lot. The pre-metrology data is saved together with an identifier for the first monitor unit. A batch is staged for the batch process including at least a first product lot including a plurality of product units together with the first monitor unit. The batch is batch processed through the batch process. After the batch processing, the first monitor unit is measured to obtain post-metrology data for the first process parameter. At least one of the post-metrology data and a difference between the post-metrology data and pre-metrology data is saved to a data file with an identifier for the first product lot or the pre-metrology data and post-metrology data is directly written to the first product lot.

Monitor data attachment to product lots for batch processes

One aspect of a semiconductor device includes an active region located in a semiconductor substrate and having an isolation region located therebetween. The active regions have corners adjacent the isolation region. An oxide layer is located over the active regions and the corners, which may also include edges of the active regions, and a ratio of a thickness of the oxide layer over the corners to a thickness of the oxide layer over the active regions ranges from about 0.6:1 to about 0.8:1. A gate is located over the active region and the oxide layer.

Semiconductor device having improved oxide thickness at a shallow trench isolation edge and method of manufacture thereof

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Allen, TX, United States of America

Damien Thomas Gilmore