STMicroelectronics

Stmicroelectronics (Crolles 2) Sas

Imec

Interuniversitair Microelektronica Centrum (Imec)

Commissariat a L'energie Atomique

Commissariat a L'energie Atomique Et Aux Energies Alternatives

Damien Lenoble

Philippe Coronel

Robin Cerutti

Thierry Schwartzmann

Laurence Boissonnet

Thomas Skotnicki

François Roy

Romain Wacquez

Aomar Halimaoui

Stéphane Monfray

Rita Rooyackers

Fabrice Lallement

Claire Fenouillett-Beranger

Isabelle Guilmeau

A region is locally modified so as to create a zone that extends as far as at least part of the surface of the region and is formed from a material that can be removed selectively with respect to the material of the region. The region is then covered with an insulating material. An orifice is formed in the insulating material emerging at the surface of the zone. The selectively removable material is removed from the zone through the orifice so as to form a cavity in place of the zone. The cavity and the orifice are then filled with at least one electrically conducting material so as to form a contact pad.

Process for producing a contact pad on a region of an integrated circuit, in particular on the electrodes of a transistor

An integrated circuit includes a bipolar transistor comprising a substrate and a collector formed in the substrate. The collector includes a highly doped lateral zone, a very lightly doped central zone and a lightly doped intermediate zone located between the central zone and the lateral zoneof the collector. The substrate includes a lightly doped lateral zone and a highly doped central zone. The dopant species in the zone of the substrate are electrically inactive.

Integrated circuit comprising a gradually doped bipolar transistor and corresponding fabrication process

A method for fabricating a semiconductor device and the device made thereof are disclosed. In one aspect, the method includes providing a substrate comprising a semiconductor material. The method further includes patterning at least one fin in the substrate, the fin comprising a top surface, at least one sidewall surface, and at least one corner. A supersaturation of point defects is created in the at least one fin. The at least one fin is annealed and then cooled down such that semiconductor atoms of the semiconductor material migrate via the point defects.

Method for fabricating a semiconductor device and the semiconductor device made thereof

A planar transistor device includes two independent gates (a first and second gates) along with a semiconductor channel lying between the gates. The semiconductor channel is formed of a first material. The channel includes opposed ends comprising dielectric zone with a channel region positioned between the gates. The dielectric zones comprises an oxide of the first material.

Transistor device with two planar gates and fabrication process

A finFET field effect transistor is produced by the formation of an electrical junction between the thin fin portion of semiconductor material which forms the channel of the transistor and the circuit substrate. Doping particles are implanted in the substrate through a mask which is then subsequently used to form the thin fin portion of the channel. The channel of the finFET transistor is thus electrically insulated from the circuit substrate in the same manner as in MOS integrated circuits realized from bulk silicon substrates.

FinFET field effect transistor insulated from the substrate

Finfet field effect transistor insulated from the substrate

Integrated circuit comprising a gradually doped bipolar transistor

A single-crystal silicon region on insulator on silicon intended to receive at least one component, the insulator having overthicknesses.

Manufacturing method of semiconductor-on-insulator region structures

A method for doping a fin-based semiconductor device is disclosed. In one aspect, the method comprises patterning at least one fin, each fin comprising a top surface and a left sidewall surface and a right sidewall surface. The method further comprises providing a first target surface being the right sidewall of a first block of material. The method further comprises scanning a first primary ion beam impinging on the first target surface with an incident angle &#x3b1; different from zero degrees and thereby inducing a first secondary ion beam, and doping at least the left sidewall surface and possibly the top surface of the fin opposite to the first target surface with the first secondary ion beam.

Method for doping a fin-based semiconductor device

An integrated circuit includes at least one photodiode associated with a transfer transistor. The photodiode is formed with an upper pn junction. The transfer transistor includes a lateral spacer located on a side facing the photodiode. An upper layer of the upper pn junction includes a lateral surface extension lying beneath the spacer. A lower layer of the upper pn junction forms a source/drain region for the transfer transistor. An edge of the lateral surface extension lying beneath the spacer and adjacent a gate of the transfer transistor contacts a substrate of the integrated circuit. An oxide layer insulating the gate from the underlying substrate does not overlie the lateral surface extension of the upper layer underneath of the lateral spacer.

Process for fabricating an integrated circuit comprising a photodiode, and corresponding integrated circuit

A method for forming, in a single-crystal semiconductor substrate of a first conductivity type, doped surface regions of the second conductivity type and deeper doped regions of the first conductivity type underlying the surface regions, including the step of negatively biasing the substrate placed in the vicinity of a plasma including, in the form of cations dopants of the first conductivity type and dopants of a second conductivity type, the dopants of the second conductivity type having an atomic mass which is greater than that of the dopants of the first conductivity type.

MOS transistor forming method

A method for forming, by thermal oxidation, a silicon oxide layer on an integrated circuit including three-dimensional silicon patterns, includes implanting a first element according to a first angle with respect to a horizontal direction. The first element is electrically neutral and has a first effect on the growth rate of a thermal oxide on silicon. A second element is implanted according to a second angle with respect to the horizontal direction. The second element is electrically neutral and has a second effect complementary to the first effect on the growth rate of a thermal oxide on silicon. The second angle is distinct from the first angle, and one of the first and second angles is a right angled. The silicon is thermally oxidized.

Silicon oxidation method

Process for fabricating a transistor comprises producing source and drain extension regions, consisting in forming a gate region on a semiconductor substrate and in implanting dopants into the semiconductor substrate on either side of and at a certain distance from the gate of the transistor. The producing of the source and drain extension regions consists in forming an intermediate layer (Cl) on the sidewalls of the gate (GR) and on the surface of the semiconductor substrate. This intermediate layer is formed from a material that is less dense than silicon dioxide. The implantation of dopants (IMP) is carried out through that part of the intermediate layer that is located on the semiconductor substrate.

Growing community of inventors

Grenoble, France

Damien Lenoble