Analog Devices,inc.

Analog Devices International Unlimited Company

Analog Devices Global

Damien Joseph McCartney

John O'Dowd

Adrian Sherry

Gabriel Banarie

Colin Gerard Lyden

Michael Byrne

David R Welland

John R Martin

Eamon Hynes

Hongxing Li

William Hunt

John M Wynne

Roberto S Maurino

Andreas Callanan

Patrick G Crowley

Kaushal Kumar Jha

Kirubakaran Ramalingam

Paraic Brannick

Jeric Adrian Butiu Monzon

Damien Murphy

Niall McGuinness

John Keane

Rabeesh Vadassery Gopinathan

Embodiments of the present disclosure may monitor and adjust a sampling rate of an ADC for converting the power signal to a digital signal, locking onto the phase and frequency of the power signal. This technique may make the sampling process coherent relative to the power signal. Properties of the power signal, such as phase, frequency, and magnitude, may be extracted relative to an idealized power signal.

Phase tracking in AC power systems using coherent sampling

Techniques for determining a state of health of an energy storage device that utilize a capacitor gain amplifier to provide an AC gain and block the DC voltage. An input capacitor can couple between an input excitation signal generator circuit and the amplifier's inverting input terminal, and a feedback capacitor can couple between the amplifier's inverting input terminal and the amplifier's output. A switch can be used to reset the feedback capacitor periodically to prevent the amplifier's output from becoming saturated from a leakage current at the inverting input terminal of the amplifier.

Techniques for determining energy storage device state of health

A charge rebalancing integration circuit can help keep an output node of a front-end integration circuit within a specified range, e.g., without requiring resetting of the integration capacitor. The process of monitoring and rebalancing the integration circuit can operate on a much shorter time base than the integration time period, which can allow for multiple charge balancing charge transfer events during the integration time period, and sampling of the integration capacitor once per integration time period, such as at the end of that integration time period. Information about the charge rebalancing can be used to adjust subsequent discrete-time signal processing, such as digitized values of the samples. Improved dynamic range and noise performance is possible. Computed tomography (CT) imaging and other use cases are described, including those with variable integration periods.

Analog/digital converter with charge rebalanced integrator

Techniques to provide calibration of a measurement system in conjunction with measurement operations. The techniques may include providing a reference device in a signal processing chain within the measurement system. An excitation signal may be driven through the reference device while it may be connected to the signal processing chain within the measurement system and a calibration response may be captured. During a measurement operation, the reference device connection may be complemented with a sensor connection in the signal processing chain and the excitation signal may be driven through the signal processing chain. A measurement response may be captured from the system. The measurement system may generate a calibrated measurement signal that accounts for phase and/or amplitude errors within the system from the calibration response and the measurement response.

Techniques for calibrating measurement systems

A digital-to-analog conversion system includes a digital-to-analog converter and an output stage for converting an output signal of the digital-to-analog converter into a voltage range. The output stage includes a first amplifier including a first input for receiving the output signal of the digital-to-analog converter, a first resistance element coupled between a second input and an output of the first amplifier, a second resistance element coupled between the second input of the first amplifier and a ground reference, and a third resistance element switchably coupled from the second input of the first amplifier to an offset voltage.

Amplifying system

A programmable gain amplifier ('PGA') may include a differential amplifier, a pair of input capacitors, a pair of feedback capacitors provided in feedback configuration about the amplifier, a first chop circuit, provided at an input of the PGA and an output of the PGA and a second chop circuit provided at an output of the PGA. The PGA also may include circuit systems to sample voltages across the input capacitors in a sampling phase. The sampled voltages may correspond to a difference between a common mode voltage of input signals to the PGA and a common mode voltage of the differential amplifier. The sampled voltage, thus, defines a common mode voltage at the amplifier's inputs during other phases of operation, when the chop circuits are operational.

Programmable gain amplifier with amplifier common mode sampling system

A capacitive sensor including a housing having a hermetically sealed cavity, a plate in the cavity, a diaphragm forming a part of the cavity and spaced from the plate, a conductive layer on the first diaphragm, and a second conductive layer on the plate, the first and second conductive layers being the electrodes of a capacitor whose capacitance varies with the position of the diaphragm relative to the plate.

Capacitive sensor

A differential capacitor one terminal capacitor interface circuit for sensing the capacitance of first and second capacitors includes a differential integrating amplifier having first and second summing nodes and an input common mode voltage; and a switching circuit for charging a first capacitor of said differential one terminal capacitor to a first voltage level and a second capacitor of said differential one terminal capacitor to a second voltage level in a first phase, in a second phase connecting said first capacitor to said first summing node and said second capacitor to said second summing node of said amplifier to provide first and second output changes substantially representative of the difference between said first and second voltage levels and said input common mode voltage, in a third phase charging said first capacitor to said second voltage level and said second capacitor to said first voltage level, and in a fourth phase connecting said first capacitor to said second summing node and said second capacitor to said first summing node of said amplifier to provide third and fourth output changes substantially representative of the difference between said first and second voltage levels and said input common mode voltage, the combined first, second, third and fourth changes representing the capacitance of said first and second capacitors substantially independent of said input common mode voltage.

One terminal capacitor interface circuit

A one terminal capacitor interface circuit for sensing the capacitance of a capacitor includes a differential integrating amplifier having an input common mode voltage and two summing nodes whose voltage is substantially equal to the input common mode voltage, a switching circuit for charging the capacitor to a first voltage level in a first phase, connecting, in a second phase, the capacitor to one of the summing nodes of the differential amplifier to provide a first output change substantially representative of the difference between the first voltage level and the input common mode voltage, and also representative of the capacitor; charging the capacitor to a second voltage level in a third phase, and connecting, in a fourth phase, the capacitor to the other summing node of the differential amplifier to provide a second output change substantially representative of the difference between the second voltage level and the input common mode voltage, and also representative of the capacitor; the combined first and second output changes representing the capacitance of the capacitor substantially independent of the input common mode voltage.

A variable capacitance switched capacitor input system and method includes a differential integrator circuit having first and second input summing nodes and a variable sensing capacitor; one terminal of the variable sensing capacitor is connected to one of the nodes in the first phase and to the other of the nodes in the second phase; an input terminal connected to a second terminal of the variable sensing capacitor receives a first voltage level in the first phase and a second voltage level in the second phase for delivering the charge on the variable sensing capacitor to the first summing node in the first phase and to the second summing node in the second phase and canceling errors in a differential integrator circuit output caused by leakage current.

Variable capacitance switched capacitor input system and method

A signal processing circuit comprising an ADC ( ) to which differential signals and pseudo-differential signals are switched through two multiplexors ( ) and ( ). Positive input signals are buffered to a positive input terminal ( ) of the ADC ( ) through a buffer ( ). Negative input signals are buffered through a conditioning circuit ( ) to a negative input terminal ( ) of the ADC ( ). The conditioning circuit ( ) comprises a buffer circuit ( ) having a buffer ( ), through which input signals are selectively buffered to the negative input terminal ( ) of the ADC ( ), and a bypass circuit ( ) which bypasses the buffer circuit ( ) for selectively passing input signals unbuffered to the negative input terminal ( ) of the ADC . First and second primary switches ( ) and ( ) are selectively operated in response to a primary switching signal from a control circuit ( ) for selecting one of the buffer circuit ( ) and the bypass circuit ( ) in response to channel select signals for the multiplexors ( ) and ( ) so that input signals, the voltage of which falls outside the operating voltage of the buffer ( ) are passed unbuffered directly to the negative input terminal ( ) through the bypass circuit ( ). The control circuit ( ) instead of being responsive to a channel select signal may be arranged to be responsive to the voltage of the input signals for operating the first and secondary primary switches ( ). Two conditioning circuits ( ) may be provided one for each input terminal to the ADC ( ).

Conditioning circuit for selectively buffering an input signal to a signal processing circuit, and a signal processing circuit incorporating the conditioning circuit

An operational amplifier having two differential input stages. A first one of the stages comprises a pair of first input transistors and another one of such stages comprises a pair of second input transistors. The second input transistors are complementary in type to the first input transistors. A comparator is fed by a sense signal and a reference signal, such sense signal being related to at least one of a non-inverting and an inverting input signal fed to the operational amplifier. The comparator produces a control signal in accordance with a difference between the sense signal and the reference signal. A switching network is responsive to the control signal and couples an output of either the first one of the stages or the second one of the stages to an output of the operational amplifier selectively in accordance with the control signal. An input chop circuit is adapted for coupling to a differential input signal, formed by the non-inverting and inverting input signals, and for providing the differential input signal with a non-inverted polarity during a first time period and such differential input signal with an inverted polarity during a succeeding time period. The differential input signal with the provided inverted polarity and the provided non-inverted polarity are fed to the coupled one of the two stages during the first time period and the succeeding time period, respectively. With such an arrangement, transitional regions where one of the stages that are coupled to the amplifier output is partially operational are eliminated, thereby reducing errors that occur in these transitional regions.

Operational amplifier

A method and circuit for providing a reference voltage to a charge balance circuit. The method includes transferring charge corresponding to V,and charge corresponding to &Dgr;V,to a summing node of the charge balance circuit, where V,is a voltage produced across a p-n junction and where &Dgr;V,is a difference between two V,voltages. With such method, instead of forming a bandgap reference circuit which produces a bandgap reference voltage and applying such voltage to the reference sampling and charge transfer circuit, charge corresponding to V,and charge corresponding to &Dgr;V,are transferred to the input summing node of the modulator in correct proportion and with a polarity corresponding to the modulator output. Thus, the reference sampling and charge transfer circuit delivers V,and &Dgr;V,charge samples to the summing node having the correct proportion and polarity, that in aggregate over a modulator cycle, equal the charge that sampling the reference voltage V,produced by the explicit bandgap reference circuits would deliver.

Bandgap reference circuit for charge balance circuits

An analog to digital conversion system having a plurality of analog to digital converters (ADCs). Each one of such ADCs is configured to convert a corresponding one of a plurality of analog signals into a corresponding sequence of digital words. The ADCs have different degrees of conversion performance. A source of the pulses is included. Each one of the ADCs is configured to provide a corresponding one of the sequences of digital words in response to the pulses. Each one of the digital words in each of the sequences is provided at substantially the same time. A controller is provided for interrupting and/or changing the configuration of one or more of the ADCs. The controller provides the interrupt and/or change in configuration with a priority to one of the ADCs over the other one of the ADCs.

Analog-to-digital conversion system

A digital filtering system is fed by input signal and produces an output signal from either a relatively low bandwidth filter or a relatively wide bandwidth filter selectively in accordance with the time rate of change in the input signal. The output signal is produced by the relatively low bandwidth filter when the input signal is slowly varying and the output signal is produced by the relatively wide bandwidth filter when the input signal changes rapidly, after which the output is produced from the relatively low bandwidth filter when the input signal reverts to its more slowly varying characteristics.

Growing community of inventors

Raheen, Ireland

Damien Joseph McCartney