International Business Machines Corporation

Damian Leo Osisek

Lisa Cranton Heller

Dan F Greiner

Charles W Gainey, Jr

Timothy John Slegel

Donald W Schmidt

Mark S Farrell

Gustav E Sittmann, Iii

Erwin F Pfeffer

Jonathan D Bradbury

Jeffrey Paul Kubala

Janet R Easton

Fadi Y Busaba

William Alan Holder

Charles Franklin Webb

Leslie W Wyman

Richard P Tarcza

Phil C Yeh

Christian Jacobi

Thomas Anthony Gregg

Peter Kenneth Szwed

Jane Helen Bartik

Patrick M West, Jr

David F Craddock

Bernd Nerz

Klaus Werner

Klaus Meissner

Hubertus Franke

Martin Schwidefsky

Tan Lu

Brenton F Belmar

Richard John Moore

Randall W Philley

Ingo Adlung

Ray Mansell

Jong Hyuk Choi

Donald William Schmidt

Anthony Saporito

Frank William Brice

Gustav E Sittman, Iii

Jonathan David Bradbury

Charles Gainey

Fadi Yusuf Busaba

Chung-Lung K Shum

Ute Gaertner

Timothy J Siegel

Mark John Lorenc

James Patrick Hennessy

Michael K Gschwind

Marcel Mitran

Elpida Tzortzatos

Bruce C Giamei

Jaya Srikrishnan

Geoffrey Owen Blandy

Christian Borntraeger

Joseph M Gdaniec

Christine M Yost

Brian L Smith

William Romney White

Thomas Michael Vail

Timothy Slegel

Louis P Gomes

Richard Victor Kisley

Mark Anthony Check

Richard K Errickson

Frank Siegfried Lehnert

John Robert Ehrman

Michael D Hocker

Peter Jeremy Relson

Ugochukwu Charles Njoku

Kenneth E Plambeck

James H Mulder

Robert R Rogers

Greg A Dyck

Carol B Hernandez

Eric David Rossman

Mike Stephen Fulton

Stephen G Wilkins

Volker Urban

Harald Freudenberger

Frank W Brice

David Paul Brelsford

Jean G Fecteau

Charles E Webb

Stephen Richard Nichols

Kevin Scott Adams

Donald P Wilton

Mark A Wisniewski

Joseph W Seigh, Ii

Tracy Ann Krein

Jean-Louis Lafitte

Melvin M Cutler

John F MacDonald

Cynthia Sittmann, Legal Representative

Daniel M Griffith

James P McCormick, Iii

Brenton Francois Belmar

Marcel M Mitran

Thomas Gregg

Mark Farrell

A method, computer program product, and computer system are provided for supporting lossless transitions between interruption and polling mode of a resource. In response to a state variable setting or a timed trigger, launching a task to process replies for a resource. The task processes each ready reply for each resource. A timed trigger is established to relaunch the task based on the task executing in polling mode. The task is exited.

Switching between polling-mode and interruption-driven modes without loss of I/O replies

An instruction is provided to perform a reset address translation protection operation when executed. Executing the instruction includes determining, by a processor, that an address translation protection bit in a specified translation table entry associated with a storage block is to be reset. Based on determining that the address translation protection bit is to be reset, executing the instruction includes resetting the address translation protection bit to deactivate write protection for the storage block. The resetting is absent waiting for an action by one or more other processors of the computing environment.

Reset dynamic address translation protection instruction

A message limit value to be used in enqueuing one or more messages on a queue of a device of the computing environment is obtained. The message limit value indicates whether an extended maximum message length is supported by the device. The extended maximum message length is different from a default maximum message length supported by the device. Based on determining that the extended maximum message length is supported and that the obtained message limit value has a defined relationship with a select value, at least one message of an extended length is enqueued on the queue of the device.

Adjunct processor extended message limit facility

In a processor supporting execution of a plurality of functions of an instruction, an instruction blocking value is set for blocking one or more of the plurality of functions, such that an attempt to execute one of the blocked functions, will result in a program exception and the instruction will not execute, however the same instruction will be able to execute any of the functions that are not blocked functions.

Function virtualization facility for blocking instruction function of a multi-function instruction of a virtual processor

Dynamic relocation of virtual machines among hypervisors in a relocation domain is provided. A hypervisor is initialized in a subdomain of the relocation domain. A record of architecture characteristics is retrieved for each hypervisor in the relocation domain. A new canonical architectural description (ARD) is created for each subdomain in the relocation domain. An effective adapter characteristic representation is created for each virtual machine defined to the hypervisor. The record of architecture characteristics for each hypervisor in the relocation domain is updated.

Live virtual machine relocation to accommodate reversible relocations in a heterogeneous cluster of hypervisor versions

Operating system deactivation of write protection for a storage block is provided absent quiescing of processors in a multi-processor computing environment. The process includes receiving an address translation protection exception interrupt resulting from an attempted write access by a processor to a storage block, and determining by the operating system whether write protection for the storage block is active. Based on write protection for the storage block not being active, the operating system issues an instruction to clear or modify translation lookaside buffer entries of the processor associated with the storage block, absent waiting for an action by another processor of multiple processors of the computing environment, to facilitate write access to the storage block proceeding at the processor.

Operating system deactivation of storage block write protection absent quiescing of processors

Selected installed function of a multi-function instruction is hidden such that even though a processor is capable of performing the hidden installed function, the availability of the hidden function is hidden such that responsive to the multi-function instruction querying the availability of functions, only functions not hidden are reported as installed.

Function virtualization facility for function query of a processor

A system and method of executing a plurality of threads, including a first thread and a set of remaining threads, on a computer processor core. The system and method includes determining that a start interpretive execution exit condition exists; determining that the computer processor core is within a grace period; and entering by the first thread a start interpretive execution exit sync loop without signaling to any of the set of remaining threads. In turn, the first thread remains in the start interpretive execution exit sync loop until the grace period expires or each of the remaining threads enters a corresponding start interpretive execution exit sync loop.

Efficiency for coordinated start interpretive execution exit for a multithreaded processor

An enhanced dynamic address translation facility product is created such that, in one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. Dynamic address translation of the virtual address proceeds. In response to a translation interruption having occurred during dynamic address translation, bits are stored in a translation exception qualifier (TXQ) field to indicate that the exception was either a host DAT exception having occurred while running a host program or a host DAT exception having occurred while running a guest program. The TXQ is further capable of indicating that the exception was associated with a host virtual address derived from a guest page frame real address or a guest segment frame absolute address. The TXQ is further capable of indicating that a larger or smaller host frame size is preferred to back a guest frame.

Creating a dynamic address translation with translation exception qualifiers

What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of a translation table of the hierarchy of translation tables are obtained. Based on the origin address, a segment table entry is obtained which contains a format control field and an access validity field. If the format control and access validity are enabled, the segment table entry further contains an access control and fetch protection fields, and a segment-frame absolute address. Store operations to the block of data are permitted only if the access control field matches a program access key provided by either a Program Status Word or an operand of a program instruction being executed. Fetch operations from the desired block of data are permitted only if the program access key associated with the virtual address is equal to the segment access control field.

Dynamic address translation with access control in an emulator environment

A system and method of implementing a wait state for a plurality of threads executing on a computer processor core of the processor. The processor is configured to execute instruction streams by the plurality of threads, wherein the plurality of threads includes a first thread and a set of remaining threads and determine that the first thread has entered a first wait state loop. The processor is also configured to determine that any of the set of remaining threads has not entered a corresponding wait state loop and remain by the first thread in the first wait state loop until each of the set of remaining threads has entered the corresponding wait state loop.

A marking capability is used to provide an indication of whether a block of memory is backing an address translation structure of a control program being managed by a virtual machine manager. By providing the marking, the virtual machine manager may check the indication prior to making paging decisions. With this information, a hint may be provided to the hardware to be used in decisions relating to purging associated address translation structures, such as translation look-aside buffer (TLB) entries.

Marking to indicate memory used to back address translation structures

Optimizations are provided for frame management operations, including a clear operation and/or a set storage key operation, requested by pageable guests. The operations are performed, absent host intervention, on frames not resident in host memory. The operations may be specified in an instruction issued by the pageable guests.

Performing an operation absent host intervention

Management of storage used by pageable guests of a computing environment is facilitated. A query instruction is provided that details information regarding the storage location indicated in the query. It specifies whether the storage location, if protected, is protected by host-level protection or guest-level protection.

Managing storage protection faults

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Vestal, NY, United States of America

Damian Leo Osisek