Micron Technology Incorporated

Dalson Ye Seng Kim

Chong Chin Hui

Roslan Bin Said

Lee Wang Lai

Lee Choon Kuan

Jeffrey Toh Tuck Fook

An assembly method is disclosed that includes providing a substrate, securing a first semiconductor device on a first surface thereof, and superimposing at least a second semiconductor device at least partially over the first semiconductor device. An outer peripheral portion of the second semiconductor device overhangs both the first semiconductor device and the substrate. Discrete conductive elements are placed between the outer peripheral portion of the second semiconductor device and a second surface of the substrate. Intermediate portions of the discrete conductive elements pass outside of a side surface of the substrate. Assemblies and packaged semiconductor devices that are formed in accordance with the method are also disclosed.

Stacked die package for peripheral and center device pad layout device

A leadframe for semiconductor components includes leadfingers, interconnect bonding sites for wire bonding to a semiconductor die, terminal bonding sites for terminal contacts for the component in an area array, and bus bars which electrically connect selected leadfingers to one another. The interconnect bonding sites are located on the leadframe relative to the bus bars such that shorting to the bus bars by wire interconnects is eliminated.

Chip on board leadframe for semiconductor components having area array

An assembly method is disclosed that includes providing a substrate, securing a first semiconductor device on a first surface thereof, and superimposing at least a second semiconductor device at least partially over the first semiconductor device is disclosed. An outer peripheral portion of the second semiconductor device overhangs both the first semiconductor device and the substrate. Discrete conductive elements are placed between the outer peripheral portion of the second semiconductor device and a second surface of the substrate. Intermediate portions of the discrete conductive elements pass outside of a side surface of the substrate. Assemblies and packaged semiconductor devices that are formed in accordance with the method are also disclosed.

Stacked device package for peripheral and center device pad layout device

A semiconductor component includes a chip on board leadframe, a semiconductor die back bonded and wire bonded to the leadframe, an encapsulant on the die and an area array of terminal contacts on the leadframe. The leadframe includes leadfingers, interconnect bonding sites for wire bonding the die, terminal bonding sites for the terminal contacts, and bus bars which electrically connect selected leadfingers to one another. The interconnect bonding sites are located on the leadframe relative to the bus bars such that shorting to the bus bars by wire interconnects is eliminated. A method for fabricating the component includes the steps of attaching the die to the leadframe, bonding the wire interconnects to the die and to the interconnect bonding sites, forming the encapsulant, and then forming the terminal contacts on the terminal bonding sites.

Growing community of inventors

Singapore, Singapore

Dalson Ye Seng Kim