International Business Machines Corporation

Cisco Technology, Inc.

Lenovo (singapore) Pte. Ltd.

Daljeet Singh

Vijoy A Pandey

Ethan M Spiegel

Ashok N Chippa

Chandramouli Radhakrishnan

Ioana M Costea

Meenakshi R Kaushik

Dar-Ren Leu

Venkatesan Selvaraj

Vipin K Garg

Robert E Zagst, Jr

John Gary Waclawsky

Nilanjan Mukherjee

Stephen Paul Belair

Kenneth A Moberg

Ronnie B Kon

Sze W Lao

A tool for partitioning a switch into one or more logical switches in a distributed system. The tool creates, by one or more computer processors, one or more logical switch routers, based, at least in part, on a user configuration. The tool assigns, by one or more computer processors, based, at least in part, on a user configuration, one or more ports to the one or more logical switch routers. The tool manages, by one or more computer processors, the one or more logical switch routers.

Logical switch architecture for network virtualization

A tool for assigning virtual port channels to one or more logical switch routers in a distributed system. The tool receives, by one or more computer processors, a request to assign a virtual port channel to a second logical switch router. The tool sends, by one or more computer processors, a request to negotiate a link-down on the channel on a first logical switch router to a universal fiber port on the first logical switch router for processing. The tool sends, by one or more computer processors, a request to create the channel on the second logical switch router to a second interface manager on the second logical switch router for processing. The tool sends, by one or more computer processors, a request to negotiate a link up on the channel on the second logical switch router to the universal fiber port on the first logical switch router for processing.

Virtual port support in a logical switch architecture

A tool for forwarding plane support in a distributed system utilizing a three-tiered architecture. The tool receives one or more messages, wherein the one or more messages include a plurality of state information. The tool determines a distribution scope for the one or more messages based, at least in part, on the plurality of state information. The tool determines a destination endpoint ID for the one or more messages, wherein the destination endpoint ID identifies one or more switch units to receive the one or more messages. The tool sends the one or more messages to a forwarding plane agent for distribution to the one or more switch units based, at least in part, on the distribution scope and the destination endpoint ID.

Abstraction layer and distribution scope for a logical switch router architecture

A tool for packet transmission and delivery in a distributed system. The tool determines a first level packet classification for one or more packets in the distributed system. The tool determines a second level packet classification for the one or more packets in the distributed system. The tool registers one or more applications included within one or more logical switch routers in the distributed system with a software module to filter the one or more packets in the distributed system.

Packet I/O support for a logical switch router architecture

A tool for forwarding plane support in a distributed system. The tool receives, by one or more computer processors, one or more messages. The tool determines, by one or more computer processors, a distribution scope for the one or more messages. The tool determines, by one or more computer processors, a destination endpoint ID for the one or more messages. The tool sends, by one or more computer processors, the one or more messages to one or more forwarding plane agents.

A networking system, and more particularly an interface management subsystem, offers logical interface abstraction for networking system software. The networking system generally transmits data via a hardware interface. All software components in the control and forwarding plane use a Logical Interface (LIF) that is a logical representation of the hardware interface. A mapping occurs between the LIF and hardware interface used to transmit the data. Each LIF is represented by an LIF identifier used to store and retrieve logical interface records to and from shared memory accessible to all protocols and applications in the control and forwarding plane. The efficient storage and retrieval of such logical interface records allows for a global unique view of network interfaces, avoidance of data replication in each networking system software application's memory space, etc.

Logical interface encoding

A method for maintaining a bridging network communication path table is presented and includes determining a failed communication link between a first bridge computer and a second bridge computer in the bridging network; identifying, in the communication path table, a first path that includes the failed communication link; and indicating that the first path is not active.

Computing forwarding tables for link failures

A tool for packet transmission and delivery in a distributed system. The tool determines one or more packets is classified as a Lpacket. The tool determines translation of the one or more packets classified as Lpackets to one or more corresponding net devices. The tool sends the one or more packets classified as a non Lpacket to a user space packet dispatcher service.

In one embodiment, a method for providing virtual link aggregation (vLAG) in a transparent interconnection of lots of links (TRILL)-enabled network, includes creating a virtual routing bridge logically connected to a first physical routing bridge and a second physical routing bridge to form a vLAG group at an edge of the TRILL-enabled network; determining a first distribution tree linking the first physical routing bridge to every other routing bridge in the TRILL-enabled network in a non-repeating fashion, ending with the second physical routing bridge; determining a second distribution tree linking the second physical routing bridge to every other routing bridge in the TRILL-enabled network in a non-repeating fashion, ending with the first physical routing bridge; receiving a multicast packet at the virtual routing bridge from one of the physical routing bridges; and distributing the multicast packet according to either the first or the second distribution tree thereby preventing looping.

Virtual link aggregation extension (vLAG+) enabled in a trill-based fabric network

In one embodiment, a system includes a TRILL-enabled network that includes a first physical routing bridge (RB) and a second physical RB, logic adapted for creating a virtual RB logically connected to the first and second physical RBs to form a vLAG group at an edge of the network, logic adapted for determining a first distribution tree linking the first physical RB to every other RB in the network in a non-repeating fashion, ending with the second physical RB, and logic adapted for determining a second distribution tree linking the second physical RB to every other RB in the network in a non-repeating fashion, ending with the first physical RB, wherein when a multicast packet is received by the virtual RB from one of the physical RBs, the multicast packet is distributed according to either the first or the second distribution tree thereby preventing looping.

Virtual link aggregation extension (VLAG+) enabled in a TRILL-based fabric network

A method and system for static routing in a TRILL network is disclosed. Routing bridges in the TRILL network use LLDP discovery to identify their next hop routing bridges. A data packet, with an inner header specifying a MAC address of a destination host, is sent by a source host and received by an ingress routing bridge. The ingress routing bridge encapsulates the data packet with a TRILL header and an outer header and sends the data packet to a next hop routing bridge on path to the destination host. The next hop routing bridge determines it is not the egress routing bridge for the data packet and sends the data packet onward to the egress routing bridge. The egress routing bridge decapsulates the data packet and forwards the data packet to the destination host specified in the inner header.

Static TRILL routing

Portions of code containing critical code routines are identified and labeled, then compiled into Dynamic Link Libraries (&ldquo;DLLs&rdquo;) and linked such that the critical code routines are optimally loaded into a reserved address space in the DLL memory space. If supported, cache locking may be enabled for the reserved address space. The portions of source code containing portions of critical code for which execution performance is to be improved are labeled, and the source code is scanned prior to compilation to locate the labeled portions of critical code. A linker is configured to store all the labeled portions of critical code into an Executable and Linking Format (&ldquo;ELF&rdquo;) section header, which is relocated at run-time into a memory space reserved for the portions of critical code. Alternatively, the critical code is compiled and linked into an executable file containing the critical code, and the executable file is optimized by scanning the instruction stream and in-lining the critical code. A prolog and an epilog that accommodates this in-lined critical code is generated, and a single optimized DLL containing the critical code is generated, which is then loaded into a reserved memory space. Robust fault containment is facilitated through the use of code modules implemented as shared libraries that can be loaded and unloaded in a running system by individual processes. These code modules can be replaced individually as defects are found and fixed without requiring replacement of the entire system image or application image. What would normally be a monolithic application is modularized, and the sharing of common code among multiple applications is facilitated.

Performance improvement of critical code execution

A system including a method and apparatus are provided for controlling fault conditions in a computer controlled device such as a data communications device. The invention can preferably be provided in a process restarter mechanism within an operation system. In operation, the process restarter system detects improper execution (i.e., detects a processing failure) of a set of instructions and initiates execution of the set of instructions in response to the operation of detecting. The system then repeats the operation of detecting and initiating according to a first restart sequence and then repeats the operation of detecting and initiating according to a second restart sequence. The second restart sequence initiates execution of the set of instructions in a different sequence than the first restart sequence. For example, the first restart sequence may perform process restarts quickly after failure detection, while the second restart sequence performs process restarts after longer and longer periods of time after failure detection. The quick restarts of the first restart sequence initially provide for maximum process uptime, and the delayed or progressively backed-off restarts allows a fault condition causing process failure to be remedied. The second restart sequence can include the use of helper processes which provide passive or active fault management. In active fault management using helper processes, the helper processes can diagnose and correct the fault condition(s) causing the improper execution of the set of instructions. Passive fault management helper processes can diagnose the fault condition and report back to the process restarter. By providing delayed restarts in the second restart sequence along with helper processes, fault management in a device equipped with the invention helps ensure proper and prolonged device operation with minimized system resource over-utilization.

Growing community of inventors

Watsonville, CA, United States of America

Daljeet Singh