Leopard Logic Inc.

Chameleon Systems, Inc.

Other

Intel Corporation

Agate Logic, Inc.

Dale Wong

Christopher E Phillips

Laurence Hager Cooke

Daniel J Pugh

Andrew Fox

Karl W Pfalzer

The present invention, generally speaking, provides a hierarchy of configuration storage. The highest level of the hierarchy is an active configuration store; the lowest level is an off-chip configuration store; in between are one or more levels of configuration stores. Every configuration is promoted from the lowest off-chip level, through each level, up to the highest active level. Each ascending level of the hierarchy has a decreasing latency time required to promote a configuration to the next higher level of the hierarchy, and a decreasing amount of available storage. This separation into levels allows the amount of available storage to be adjusted depending on the inherent latency of the level's storage mechanism, where a longer latency requires a larger cache. This in turn allows the total required storage for a given performance level to be minimized.

Hierarchical storage architecture for reconfigurable logic configurations

A Field Programmable Gate Array (FPGA) core cell with one or more Look-Up Tables (LUTs) and a selectable logic gate is presented as a space-efficient alternative to the conventional LUT-based FPGA core cell. An algorithm based upon the familiar FlowMap algorithm for LUT-based FPGA core cells implements the mapping of a Boolean logic network into the disclosed FPGA core cell.

Field programmable gate array core cell with efficient logic packing

An interconnection network architecture which provides an interconnection network which is especially useful for FPGAs is described. Based upon Benes networks, the resulting network interconnect is rearrangeable so that routing between logic cell terminals is guaranteed. Upper limits on time delays for the network interconnect are defined and pipelining for high speed operation is easily implemented. The described network interconnect offers flexibility so that many design options are presented to best suit the desired application.

Interconnection network for a field programmable gate array

A programmable interface for FPGA cores embedded in an integrated circuit. The interface has an interconnect multiplexer (which includes demultiplexers) connected to the FPGA core and other elements of the integrated circuit. A control portion of the interface provides selection control bits to the interconnect multiplexer to make the desired connection configuration. Programmable latches in the control portion hold the selection bits which are loaded into the latches at the same time configuration bits are loaded into the integrated circuit to program the FPGA core. Alternatively, the control portion can be implemented by another FPGA core which is configured as a state machine to generate the selection control bits.

Programmable interface for field programmable gate array cores

A computer implemented method for automatically compiling a computer program written in a high level programming language into an intermediate data structure. The data structure is analyzed to identify critical blocks of logic, which can be implemented as an application specific integrated circuit (ASIC), to improve overall performance. The critical blocks of logic are transformed into new equivalent logic with maximal data parallelism. The parallelized logic is then translated into a Boolean gate representation, which is suitable for implementation on an ASIC. The ASIC may be coupled with a generic microprocessor via custom instruction for the microprocessor. The original computer program is then compiled into object code with the new expanded target instruction set.

Method for compiling high level programming languages into embedded microprocessor with multiple reconfigurable logic

An integrated circuit which contains a processor, and configurable logic with configuration memory such that the configurable logic can emulate a large memory array when the contents of the array are very sparse. This structure allows for fast access and a continuous updating capability while remaining internal to the chip. A methodology for recompressing the contents of the configurable logic while updating the configurable logic is also described.

Reconfigurable logic for table lookup

A system and method of logic synthesis uses a behavioral synthesis tool to convert a behavioral language description (e.g., behavioral description code, an intuitive algorithm, or programming language description) of an ASIC into a partitioned RTL language description including RTL sub-descriptions corresponding to each of control, datapath, and memory. Each of the higher level RTL sub-descriptions is then mapped directly (i.e., a one-to-one mapping correspondence) to re-configurable silicon structures without requiring an RTL synthesis tool to translate the RTL description into individual standardized cell logic gates and interconnect level description. The silicon structures are controlled by the RTL sub-descriptions to provide a direct synthesized physical implementation of the ASIC thereby providing a single step synthesis method of going from a behavioral description to a synthesized silicon implementation.

Behavioral silicon construct architecture and mapping

The present invention, generally speaking, provides a reconfigurable computing solution that offers the flexibility of software development and the performance of dedicated hardware solutions. A reconfigurable processor chip includes a standard processor, blocks of reconfigurable logic (,), and interfaces (,) between these elements. The chip allows application code to be recompiled into a combination of software and reloadable hardware blocks using corresponding software tools. A mixture of arithmetic cells and logic cells allows for higher effective utilization of silicon than a standard interconnect. More efficient use of configuration stack memory results, since different sections of converted code require different portions of ALU functions and bus interconnect. Many types of interfaces with the embedded processor are provided, allowing for fast interface between standard processor code and configurable &ldquo;hard-wired&rdquo; functions.

Integrated processor and programmable data path chip for reconfigurable computing

A reconfigurable processor chip has a mixture of reconfigurable arithmetic cells and logic cells for higher effective utilization than a standard FPGA. The reconfigurable processor includes a standard microprocessor such as an embedded RISC processor. Many different types of interfaces are used to interface between the embedded processor and the reconfigurable portions of the chip, thus allowing for the fastest interface between standard processor code and configurable 'hard-wired' functions. A configuration memory stack is provided, allowing for nearly instantaneous reconfiguration. if desired, configuration planes can be shared between ALU function configuration and bus interconnect configuration, allowing more efficient use of stack memory.

Integrated processor and programmable data path chip for reconfigurable

A method is presented for automatically compiling a high level computer program down into an application specific integrated circuit coupled with a generic microprocessor. The original source code is written in a standard programming language such as ANSI C. Source code analysis is performed by our compiler to automatically determine which blocks of logic are most appropriate for the application specific integrated circuit and which for the generic microprocessor. The complete layout of the application specific integrated circuit is automatically generated by our compiler. Object code for the microprocessor, with custom instructions to invoke the application specific integrated circuit, is also automatically generated by our compiler.

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San Francisco, CA, United States of America

Dale Wong