Ati Technologies Ulc

Ati International Srl

Advanced Silicon Technologies LLC

Dale R Jurich

Stephen C Purcell

John S Yates, Jr

Sandeep Nijhawan

Korbin S Van Dyke

Shalesh Thusoo

Niteen Aravind Patkar

Matthew F Storch

Gurjeet Singh Saund

David L Reese

Paul H Hohensee

Paul Campbell

A multi-instruction set architecture (ISA) computer system includes a computer program, a first processor, a second processor, a profiler, and a translator. The computer program includes instructions of a first ISA, the first ISA having a first complexity. The first processor is configured to execute instructions of the first ISA. The second processor is configured to execute instructions of a second ISA, the second ISA being different than the first ISA and having a second complexity, wherein the second complexity is less than the first complexity. The profiler is configured to select a block of the computer program for translation to instructions of the second ISA, wherein the block includes one or more instructions of the first ISA. The translator is configured to translate the block of the first ISA into instructions of the second ISA for execution by the second processor.

Apparatus for executing programs for a first computer architecture on a computer of a second architecture

Executing programs coded in an instruction set of a first computer on a computer of a second, different architecture. An operating system maintains an association between each one of a set of concurrent threads and a set of computer resources of the thread's context. Without modifying a pre-existing operating system of the computer, an entry exception is establishing to be raised on each entry to the operating system at a specified entry point or on a specified condition. The entry exception has an associated entry handler programmed to save a context of an interrupted thread and modify the thread context before delivering the modified context to the operating system. A resumption exception is established to be raised on each resumption from the operating system complementary to one of the specified entries. The resumption exception has an associated exit handler programmed to restore the context saved by a corresponding execution of the entry handler. The entry exception, exit exception, entry handler, and exit handler are cooperatively designed to maintain an association between a one of the threads and an extended context of the thread through a context change induced by the operating system, the extended context including resources of the computer associated with the thread beyond those resources whose association with the thread is maintained by the operating system.

Apparatus for executing programs for a first computer architechture on a computer of a second architechture

Executing programs for a first computer architecture on a computer of a second architecture

A computer concurrently executes a first operating system coded in a RISC instruction set and a second operating system coded in a CISC instruction set. When an exception is raised while executing a program coded in the RISC instruction set, an execution thread may be initiated under the CISC operating system. The exception may be delivered to the initiated thread for handling by the CISC operating system.

System for delivering exception raised in first architecture to operating system coded in second architecture in dual architecture CPU

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Los Gatos, CA, United States of America

Dale R Jurich