Nvidia Corporation

3dlabs Inc., Ltd.

Intergraph Corporation

Dale L Kirkland

Ziyad Sami Hakura

Emmett Michael Kilgariff

Cynthia Ann Edgeworth Allison

Yury Y Uralsky

Jeffrey A Bolz

Steven James Heinrich

James Leroy Deming

Eric Brian Lum

Patrick Richard Brown

Karim Abdalla

Rouslan Lyubomirov Dimitrov

Walter Robert Steiner

Johnny S Rhoades

Cynthia Allison

Henry Packard Moreton

Jack H Choquette

Rui Manuel Bastos

Tyson J Bergland

Clifford A Whitmore

Matt E Buckelew

Pierre Souillot

Timothy S Johnson

Sachin Satish Idgunji

Siddharth Sharma

Joseph Clay Terry

Steven E Molnar

Jonah Matthew Alben

Michael C Shebanow

Alexander Lev Minkin

James D Kelly

Christian Rouet

Vernon R Brethour

Jeffrey Scott Ford

Gary Warren Shelton

William Craig McKnight

William Lazenby

James Paul Turner

David Charles Patrick

Cynthia E Allison

Karl M Wurstner

Jerome Francis Duluk, Jr

Mark J Kilgard

Lacky V Shah

Sean Jeffrey Treichler

Joel James McCormack

Philip Browning Johnson

Amit Jain

Robert Ohannessian

Timothy John Purcell

Christian Amsinck

Gregory Scott Palmer

Andrei Khodakovsky

Stewart G Carlton

Mark Allen Mosley

Harald Jean Smit

Michael S Farmer

Gernot Schaufler

Cyril Jean-Francois Crassin

Joseph Detmer

Don Bittel

Steve Conklin

Gary Shelton

William R Lazenby, Jr

Haren Kethareswaran

Jeff Bolz

Allen Jensen

Niket Agrawal

Joseph Cavanaugh

Matthew C Quinn

Graphics processing unit (GPU) performance and power efficiency is improved using machine learning to tune operating parameters based on performance monitor values and application information. Performance monitor values are processed using machine learning techniques to generate model parameters, which are used by a control unit within the GPU to provide real-time updates to the operating parameters. In one embodiment, a neural network processes the performance monitor values to generate operating parameters in real-time.

Real-time hardware-assisted GPU tuning using machine learning

Attributes of graphics objects are processed in a plurality of graphics processing pipelines. A streaming multiprocessor (SM) retrieves a first set of parameters associated with a set of graphics objects from a first set of buffers. The SM performs a first set of operations on the first set of parameters according to a first phase of processing to produce a second set of parameters stored in a second set of buffers. The SM performs a second set of operations on the second set of parameters according to a second phase of processing to produce a third set of parameters stored in a third set of buffers. One advantage of the disclosed techniques is that work is redistributed from a first phase to a second phase of graphics processing without having to copy the attributes to and retrieve the attributes from the cache or system memory, resulting in reduced power consumption.

Power efficient attribute handling for tessellation and geometry shaders

A graphics processing pipeline includes three architectural features that allow a fragment shader to efficiently calculate per-sample attribute values using barycentric coordinates and per-vertex attributes. The first feature is barycentric coordinate injection to provide barycentric coordinates to the fragment shader. The second feature is an attribute qualifier that allows an attribute of a graphics primitive to be processed without conventional fixed-function interpolation. The third feature is a direct access path from the fragment shader to triangle data storage hardware resources where vertex attribute data and/or plane equation coefficients are stored. Allowing the fragment shader to calculate per-sample attribute values in this way advantageously increases system flexibility while reducing workload associated with triangle plane equation setup.

System-generated stable barycentric coordinates and direct plane equation access

A tile coalescer within a graphics processing pipeline coalesces coverage data into tiles. The coverage data indicates, for a set of XY positions, whether a graphics primitive covers those XY positions. The tile indicates, for a larger set of XY positions, whether one or more graphics primitives cover those XY positions. The tile coalescer includes coverage data in the tile only once for each XY position, thereby allowing the API ordering of the graphics primitives covering each XY position to be preserved. The tile is then distributed to a set of streaming multiprocessors for shading and blending operations. The different streaming multiprocessors execute thread groups to process the tile. In doing so, those thread groups may perform read-modify-write operations with data stored in memory. Each such thread group is scheduled to execute via atomic operations, and according to the API order of the associated graphics primitives.

Techniques for maintaining atomicity and ordering for pixel shader operations

A multi-pass unit interoperates with a device driver to configure a screen space pipeline to perform multiple processing passes with buffered graphics primitives. The multi-pass unit receives primitive data and state bundles from the device driver. The primitive data includes a graphics primitive and a primitive mask. The primitive mask indicates the specific passes when the graphics primitive should be processed. The state bundles include one or more state settings and a state mask. The state mask indicates the specific passes where the state settings should be applied. The primitives and state settings are interleaved. For a given pass, the multi-pass unit extracts the interleaved state settings for that pass and configures the screen space pipeline according to those state settings. The multi-pass unit also extracts the interleaved graphics primitives to be processed in that pass. Then, the multi-pass unit causes the screen space pipeline to process those graphics primitives.

Multi-pass rendering in a screen space pipeline

One embodiment of the present invention includes a technique for distributing work slices associated with a graphics processing unit for processing. A primitive distribution system receives a draw command related to a graphics object associated with a plurality of indices. The primitive distribution system creates a plurality of work slices, where each work slice is associated with a different subset of the indices included in the plurality of indices. The primitive distribution system scans a first subset of indices to identify a first set of characteristics that is needed to process a second subset of indices. The primitive distribution system processes the second subset of indices based at least in part on the one or more characteristics. Advantageously, because multiple work slices are analyzed in parallel for duplicate indices, the time required to analyze work slices is more in balance with the time required to process the work slices, leading to greater utilization of GPU resources and improved overall performance.

Distributed index fetch, primitive assembly, and primitive batching

One embodiment of the present invention includes a graphics subsystem that includes a tiling unit, a crossbar unit, and a screen-space pipeline. The crossbar unit is configured to transmit primitives interleaved with state change commands to the tiling unit. The tiling unit is configured to record an initial state associated with the primitives and to transmit to the screen-space pipeline one or more primitives in the primitives that overlap a first cache tile. The tiling unit is further configured to transmit the initial state to the screen-space pipeline and to transmit to the screen-space pipeline one or more primitives in the primitives that overlap a second cache tile. The tiling unit includes a state filter block configured to determine that a first state change in the state change commands is followed by a second state change, without an intervening primitive, and to forego transmitting the first state change in response.

State handling in a tiled architecture

One embodiment of the present invention sets forth a technique for managing graphics processing resources in a tile-based architecture. The technique includes storing a release packet associated with a graphics processing resource in a buffer and initiating a replay of graphics primitives stored in the buffer and associated with the graphics processing resource. The technique further includes, for each tile included in a plurality of tiles and processed during the replay, reading the release packet and determining whether the tile is a last tile processed during the replay. The technique further includes determining not to transmit the release packet to a screen-space pipeline and continuing to read graphics data stored in the buffer if the tile is not the last tile to be processed during the replay, or transmitting the release packet to the screen-space pipeline if the tile is the last tile to be processed during the replay.

Techniques for managing graphics processing resources in a tile-based architecture

One embodiment of the present invention sets forth a graphics subsystem configured to implement distributed cache tiling. The graphics subsystem includes one or more world-space pipelines, one or more screen-space pipelines, one or more tiling units, and a crossbar unit. Each world-space pipeline is implemented in a different processing entity and is coupled to a different tiling unit. Each screen-space pipeline is implemented in a different processing entity and is coupled to the crossbar unit. The tiling units are configured to receive primitives from the world-space pipelines, generate cache tile batches based on the primitives, and transmit the primitives to the screen-space pipelines. One advantage of the disclosed approach is that primitives are processed in application-programming-interface order in a highly parallel tiling architecture. Another advantage is that primitives are processed in cache tile order, which reduces memory bandwidth consumption and improves cache memory utilization.

Distributed tiled caching

Growing community of inventors

Madison, AL, United States of America

Dale L Kirkland