Intel Corporation

Dale J Juenemann

James A Boyd

R Scott Tetrick

Glenn J Hinton

Robert J Royer, Jr

Oscar P Pinto

Paul S Diefenbaugh

Francis Corrado

Scott Burridge

Robert J Brennan

Sanjeev N Trika

Pranav Kalavade

Steven E Wells

Frank T Hady

Anand S Ramalingam

Lily Pao Looi

Zvika Greenfield

Chia-Hung Sophia Kuo

Amber D Huffman

Raymond Scott Tetrick

Jeanna N Matthews

Curtis Edward Jutzi

Thomas J Barnes

Assar Badri

Scott R Tetrick

Jordan Howes

Gary C Chow

Examples include techniques for emulating a non-volatile dual inline memory module (NVDIMM) in a computing platform using a non-volatile storage device. When a power up event occurs for the computing platform, a host memory buffer may be allocated in a system memory device and a backing store for the host memory buffer may be copied from the non-volatile storage device to the host memory buffer in the system memory device. When a power down event or a flush event occurs for the computing platform, the host memory buffer may be copied from the system memory device to the corresponding backing store for the host memory buffer in the non-volatile storage device. Thus, virtual NVDIMM functionality may be provided without having NVDIMM hardware in the computing platform.

NVDIMM emulation using a host memory buffer

A method is described. The method includes receiving notice of a page fault. A page targeted by a memory access instruction that resulted in the page fault residing in persistent memory without system memory status. In response to the page fault, updating page table information to include a translation that points to the page in persistent memory such that the page changes to system memory status without moving the page and system memory expands to include the page in persistent memory.

Fast page fault handling process implemented on persistent memory

Technologies for protecting data in an asymmetric volume (ASV) that includes a first storage device that supports device-based encryption and a second storage device that does not support device-based encryption. In embodiments the technologies enable disparate capabilities of the storage devices in an ASV to be exposed to a user. When a complete copy of targeted data identified by a user input for encrypted storage is not present on the first storage device, at least a portion of the targeted data stored on the second storage device is rewritten to the first storage device. When a complete copy of the targeted data is stored on the first storage device, one or more security operations are performed to obfuscate or erase any portion of the targeted data stored on the second storage device.

Technologies for protecting data in an asymmetric storage volume

A host based caching technique may be used to determine caching policies for a hybrid hard disk drive. Because the host based caching may make use of knowledge about what data is being cached, improved performance may be achieved in some cases.

Host controlled hybrid storage device

Techniques are disclosed for programming memory devices such as solid-state drives. In an embodiment, a memory controller is configured to execute a programming sequence that interleaves coarse and fine tuning steps for neighboring word lines. In one example, three consecutive word lines are programmed in six steps. At step 1, word line n is coarse programmed to an intermediate voltage level; at step 2, word line n+1 is coarse programmed to an intermediate voltage level; at step 3, word line n is fine programmed to its target voltage level; at step 4, word line n+2 is coarse programmed to an intermediate voltage level; at step 5, word line n+1 is fine programmed to its target voltage level; at step 6, word line n+2 is fine programmed to its target voltage level. No reads are allowed until all cell levels are programmed. Phase change memory may be used as staging buffer.

Interleaved all-level programming of non-volatile memory

Systems and techniques for control of storage device power states are described herein. In some embodiments, a control system for a storage device of a computing device may include receiver logic to receive a proximity signal indicative of a distance of a user from a proximity sensor, transition logic to determine that the proximity signal satisfies out-of-proximity criteria and generate an out-transition signal based at least in part on the determination that the proximity signal satisfies the out-of-proximity criteria, and state-change logic to cause a change in a power state of the storage device from a first power state to a second power state, in response to the out-transition signal, wherein the storage device consumes less power in the second power state than in the first power state. Other embodiments may be described and/or claimed.

Systems and techniques for control of storage device power states

A method which includes initiating a power management policy based on a processing element for a computing platform entering a given power state. The power management policy includes a determination as to whether an input/output (I/O) controller and a memory controller for the computing platform are substantially quiescent. The computing platform may then be transitioned to a low power system state from a run power system state based on a determination that both the I/O controller and the memory controller are substantially quiescent and an indication that the computing platform is capable of entering the low power system state. According to this method, the low power system state includes entering one or more devices responsive to the computing platform in a power level adequate to retain a configuration state that enables the one or more devices to transition back to the run power system state in a manner that is substantially transparent to an operating system for the computing platform. Other implementations and examples are also described in this disclosure.

Transitioning a computing platform to a low power system state

In some embodiments, an electronic system may include a cache located between a mass storage and a system memory, and code stored on the electronic system to prevent storage of stream data in the cache and to send the stream data directly between the system memory and the mass storage based on a comparison of first metadata of a first request for first information and pre-boot stream information stored in a previous boot context. Other embodiments are disclosed and claimed.

Apparatus and method for cache utilization

In some embodiments, a non-volatile cache memory may include a multi-level non-volatile cache memory configured to be located between a system memory and a mass storage device of an electronic system and a controller coupled to the multi-level non-volatile cache memory, wherein the controller is configured to control utilization of the multi-level non-volatile cache memory. Other embodiments are disclosed and claimed.

Apparatus and method for multi-level cache utilization

In some embodiments, a processor-based system includes a processor, a system memory coupled to the processor, a mass storage device, a cache memory located between the system memory and the mass storage device, and code stored on the processor-based system to cause the processor-based system to utilize the cache memory. The code may be configured to cause the processor-based system to preferentially use only a selected size of the cache memory to store cache entries having less than or equal to a selected number of cache hits. Other embodiments are disclosed and claimed.

Apparatus and method for low touch cache management

In some embodiments, a non-volatile cache memory may include a segmented non-volatile cache memory configured to be located between a system memory and a mass storage device of an electronic system and a controller coupled to the segmented non-volatile cache memory, wherein the controller is configured to control utilization of the segmented non-volatile cache memory. The segmented non-volatile cache memory may include a file cache segment, the file cache segment to store complete files in accordance with a file cache policy, and a block cache segment, the block cache segment to store one or more blocks of one or more files in accordance with a block cache policy, wherein the block cache policy is different from the file cache policy. The controller may be configured to utilize the file cache segment in accordance with information related to the block cache segment and to utilize the block cache segment in accordance with information related to the file cache segment. Other embodiments are disclosed and claimed.

Apparatus and method for segmented cache utilization

A method and system to perform caching based at least on one or more file-level heuristics. The caching of a storage medium in a caching device is performed by a cache policy engine. The cache policy engine receives file-level information of input/output access of data of the storage medium and caches or evicts the data of the storage medium in the caching device based on the received file-level information. By utilizing information about the files and file operations associated with the disk sectors or logical block addresses of the storage medium, the cache policy engine can make a better decision on the data selection of the storage medium to be cached in or evicted from the caching device in one embodiment of the invention. Higher cache hit rates can be achieved and the performance of the system utilizing the cache policy engine is improved.

Method and system to perform caching based on file-level heuristics

Methods and apparatus to detect a data mining process are presented. In one embodiment the method comprising monitoring access of a process to a resource and classifying if the process is a data mining process based on at least one of a plurality of monitored values, such as an access rate, an eviction rate, and an I/O consumption value.

Growing community of inventors

North Plains, OR, United States of America

Dale J Juenemann