Hewlett-packard Development Company, L.p.

Compaq Computer Corporation, Inc.

Dale Hayward Hall

Nevine Nassif

James Arthur Farrell

Madhav Desai

Gill Watt

A system for accurately determining Elmore delays in DCVSL structures is disclosed. The system uses circuit simulation to determine models for Elmore delays through devices within specific circuit structures. The circuit structures include DCVSL circuits to accurately model performance of devices with such a structure. The system also determines discharge characteristics for DCVSL circuits using simulation. In order to determine Elmore delays, the system analyzes a circuit representation to locate DCVSL structures. The discharge characteristics and models are used to determine Elmore delays for each structure located.

Method and apparatus for performing timing verification of a circuit

A system for rapidly accurate Elmore delays is disclosed which uses circuit simulations with different circuit configurations to generate Elmore delay models. From data generated by the simulations, Elmore delays are represented as functions of a capacitance charge and device width for a variety of device configurations. Similarly, accurate capacitance models are determined for each device. To determine an Elmore delay for a discharge path, the appropriate models are applied to each device and summed together. Within a timing verifier, the present invention can rapidly determine critical paths which require additional consideration.

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Northborough, MA, United States of America

Dale Hayward Hall