Agere Systems Inc.

Lucent Technologies Inc.

At&t Bell Laboratories

Agere Systems Guardian Corp.

Bell Telephone Laboratories

At&t Ipm Corp.

Lucent Techmologies Inc.

Dale Harvey Nelson

Lizhong Sun

Zhigang Ma

Kouros Azimi

Brian Albert Wittman

Wenzhe Luo

Paul C Davis

Harold Simmonds

Joseph J Nahas

Raymond G Jackson

Tseng-Nan Tsai

William Eric Holland

Xiangqun Sun

DeWitt G Ong

John M Khoury

Douglas D Lopata

Jeffrey Paul Grundvig

Richard Lawrence McDowell

Carl R Stevenson

Parag Parikh

Timothy Noonan Comerford

Iconomos A Koullias

Rajeev Krishnamoorthy

Thayamkulangara R Viswanathan

Oceager P Yee

Peter S Bernardson

Brian J Petryna

Donald H Friedberg

Xiqun Zhu

Pamela C Kwong

Lai Q Pham

Thomas A Gentles

A buffer circuit includes an input stage including at least one MOS device having a first threshold voltage associated therewith, the input stage being adapted to receive an input signal referenced to a first voltage supply. The buffer circuit further includes an output stage including at least one MOS transistor having the first threshold voltage associated therewith, an input of the output stage being connected to an output of the input stage, the output stage being operative to generate an output signal which is indicative of a logic state of the input signal. The buffer circuit includes a delay control circuit adapted for connection between at least one of the first voltage supply and a voltage return of the buffer circuit, and at least one of the input stage and the output stage. The delay control circuit includes at least one MOS device having a second threshold voltage associated therewith. The MOS device in the delay control circuit being adapted to receive, as a control signal, a second voltage supply, a delay of the buffer circuit being at least partially controlled as a function of a process parameter, the second voltage supply and/or a temperature of the MOS device in the delay control circuit.

Enhanced delay matching buffer circuit

A signal generator circuit includes an oscillator operative to generate a first signal having a first frequency associated therewith, and a phase stepper circuit coupled to the oscillator. The phase stepper circuit is configured to receive a plurality of control signals indicative of respective phases of the first signal, and to generate a second signal as a function of the plurality of control signals. The second signal has a second frequency associated therewith that is a fractional multiple or a fractional division of the first frequency. The second signal has a phase associated therewith which changes with periods of the second signal.

Signal generator circuit having multiple output frequencies

A signal generator circuit having enhanced control resolution includes a variable frequency oscillator having a first control input adapted to receive a first signal and at least a second control input adapted to receive a second signal. The second signal is afforded a weight which is substantially equal to a weight of a least significant bit of the first signal. The variable frequency oscillator is operative to generate an output signal having a frequency which varies as a function of the first and second signals. The signal generator circuit further includes a first counter, a first divider and a modulation circuit. The first counter is configurable for generating an output count based at least in part on a difference between a third signal presented to the signal generator circuit and a fourth signal indicative of the output signal, the output count including the first signal. The first divider has a selectable divide value associated therewith and is configurable for receiving the output signal and for generating the fourth signal based on the divide value. The modulation circuit is adapted to receive at least a portion of the output count and the fourth signal and to generate the second signal as a function of the output count and the fourth signal.

Digitally controlled oscillator having enhanced control resolution

A baseband clock synthesizer having particular use in a BLUETOOTH piconet device, having the capability of generating either 12 MHz or 13 MHz clock signals generated from any reference clock signal, e.g., 12.00, 12.80, 13.00, 15.36, 16.80, 19.20, 19.44, 19.68, 19.80, and 26.00 MHz. A fractional-N frequency divider is implemented with a PLL including a variable divider allowing the use of virtually any reference frequency input to generate a locked 156 MHz clock signal used as a basis for a 12 MHz or 13 MHz baseband clock signal. A residue feedback sigma-delta modulator provides a varying integer sequence to an integer divider in a feedback path of the PLL, effectively allowing division by non-integer numbers in the PLL. Thus, the PLL can be referenced to virtually any reference clock and still provide a fixed output clock signal (e.g., 12 or 13 MHz).

Fractional-N baseband frequency synthesizer in bluetooth applications

This disclosure relates to a cell-placeable variable-frequency digitally controlled oscillator (DCO) that consumes approximately the same current in a fast process corner as in the case of a slow process corner. By modulating the effective channel length of transistors in inverters, a fast process DCO may be slowed down to a desired frequency at nearly the same current consumption as that of a slow process DCO.

Digitally controlled oscillator for reduced power over process variations

A phase-locked loop includes a variable frequency generator, a comparator and a counter. The variable frequency generator is configurable for generating an output signal having a frequency which varies based at least in part on at least first and second control signals presented thereto. The comparator is configurable for receiving a first signal and a second signal, the first signal being an input signal presented to the phase-locked loop and the second signal being representative of the output signal from the variable frequency generator. The comparator generates a difference signal representative of a difference between a phase and/or a frequency of the first and second signals, the difference signal comprising the first control signal. The counter is configurable for generating an output count based at least in part on the difference signal from the comparator. The output count is a digital representation of the difference signal, the output count comprising the second control signal. The frequency of the output signal from the variable frequency generator is determined as a function of the difference signal and the output count.

Digital phase-locked loop

A telephone line-powered power supply, a method of operating the same and telephone line-powered ancillary equipment. In one embodiment, the power supply includes: (1) a transformer having a primary winding and a secondary winding and (2) an energy storage device (which may, but is not required to, be a capacitor) series-coupled to the primary winding, the primary winding and the energy storage device adapted to be coupled to, and provide a terminating resistance for, a telephone line. A node between the primary winding and the energy storage device provides DC power. Another embodiment employs a control switch to regulate an energy storage device, thereby dispensing with a need for the transformer.

Telephone line-powered power supply for ancillary equipment and method of operation thereof

Sampling noise in an analog signal output from a codec, such as a speech codec, is reduced using linear interpolation. The output of a codec is input into two sample and hold circuits. The circuits generate two output signals (i.e. voltages) for each input signal. One of the output signals represents an interpolated signal located midway between an historical output signal and input signal. The generation of interpolated output signals reduces sampling noise.

Methods and devices for reducing sampling noise in analog signals using linear interpolation

A phase-locked loop (PLL) circuit having a voltage-controlled oscillator (VCO) is automatically calibrated for VCO center frequency and VCO gain during power up or responsive to a calibration signal. The VCO has several input voltage versus output frequency operating curves. During a calibration phase, proper VCO center frequency is selected by selecting one of the operating curves. VCO gain is then determined using the selected VCO operating curve. If the value of VCO gain is not within predetermined limits, VCO gain is adjusted accordingly, and the process of selecting a VCO operating curve and determining VCO gain is repeated.

VCO gain self-calibration for low voltage phase lock-loop applications

A phase-lock loop (PLL) circuit provides fast locking and low spurious modulation jitter through &ldquo;gearshifting&rdquo; control. The gearshifting PLL combines the advantages of low jitter from integer-N PLL and fast locking from fractional-N PLL. The PLL circuit includes a phase/frequency detector, a charge pump, a loop filter, and a voltage controlled oscillator (VCO). Control of the PLL circuit includes configuring the PLL circuit in two configurations, one for each phase of operation. The bandwidth of the loop filter is increased during the first phase of operation and the circuit is locked to a frequency that is close to the desired output frequency. During the second phase, the bandwidth of the loop filter is decreased and the circuit is locked to the desired frequency. The first configuration provides a relatively fast lock time compared to the lock time provided by the second configuration. The second configuration provides more stability than the first configuration.

Low-noise, fast-lock phase-lock loop with &ldquo;gearshifting&rdquo; control

A ring oscillator including a voltage-to-current converter for producing at least one control current from at least one control voltage and, a plurality of delay cells coupled to the converter, wherein at least one output of the one of the delay cells is coupled to the input of another of the delay cells, wherein the voltage-to-current converter produces a substantially linear output when the at least one control voltage is varied between zero volts and a rail supply voltage. Since the ring oscillator operates from a low voltage source, it can be used in applications where power supply (e.g., battery size) is small (e.g., pagers, cellular phone applications).

Low voltage differential voltage-controlled ring oscillator

A method and lock detector for detecting lock between a reference signal and a feedback signal of a PLL circuit. A number of clock cycles of the feedback signal is counted during consecutive test intervals defined by the reference signal. A feedback comparator determines whether the number of clock cycles of the feedback signal during a given test interval is within an expected range. Before lock has been indicated, a qualification counter is either incremented or reset after each test interval in accordance with the expected range determination. A lock indication signal indicating that lock has been achieved is provided if said qualification counter exceeds a qualification threshold.

Lock detector for phase-locked loop

An integrated circuit has a phase-locked loop (PLL) frequency synthesizer circuit which has a charge pump circuit for providing an output control voltage to adjust an oscillator frequency in response to fast and slow signals provided by a phase detector. The charge pump circuit has first and second current sources, and a switching network for selectively coupling, in response to said fast signal, the first current source to one of an internal node and an output node coupled to an output capacitor and having an output voltage, and, in response to said slow signal, the second current source to one of the internal node and the output node. The charge pump circuit has first and second unity gain buffers coupled in parallel at their inputs to the output node and at their outputs to the internal node, wherein the first buffer is configured to have a voltage tracking range approximately up to a positive supply rail and the second buffer is configured to have a voltage tracking range approximately down to a negative supply rail, wherein the voltage tracking ranges of said buffers overlap each other, to provide an overall substantially rail-to-rail voltage tracking range.

Charge pump for low-voltage, low-jitter phase locked loops

A highly accurate tuning circuit for a tunable filter is provided which trims an RC time constant based on variances in both a formed capacitive component as well as variances in formed resistive components. A capacitor and resistor based tuning control circuit includes both a formed capacitor based tuning reference current generator and a formed resistor based tuning voltage reference generator. Each generates a voltage reference which is compared to the other to determine control signals for tuning a tunable resistive component forming the resistive portion of the RC time constant of the relevant filter. The resistive component is tuned by shorting selective resistors in the tunable resistive component. By tuning the RC time constant to the particular variances in capacitor and resistor components formed in the integrated circuit, the RC time constant of the tunable filter can be tuned to a desired absolute value within a tighter tolerance range than was previously available with conventional tuning circuits which provided tuning control based only on the variances of formed resistor elements.

Growing community of inventors

Shillington, PA, United States of America

Dale Harvey Nelson