International Business Machines Corporation

Marvell Asia Pte., Ltd.

Globalfoundries Inc.

Dale E Pontius

John Atkinson Fifield

Eric D Hunt-Schroeder

Billy J Knowles

Toshiaki Kirihata

David B Rolfe

Christine M Desnoyers

Clive A Collins

Louis Lu-Chen Hsu

Minh H Tong

Christopher P Miller

Gregory J Fredeman

Steven William Tomashot

Endre P Thoma

Steven Michael Eustis

Chorng-Lii Hwang

Robert Tamlyn

Michael A Roberge

Edward J Nowak

Claude Louis Bertin

Harold Pilo

Timothy Jay Dell

Howard L Kalter

Darren Lane Anand

Kevin William Gorman

Thomas M Maffitt

Bruce G Hazelzet

Kenneth E Beilstein, Jr

Marc Raymond Faucher

Francis H Chan

Gordon A Kelley, Jr

Donald W Price

Geordie M Braceras

Nathan R Hiltebeitel

Yee-Ming Ting

Willem B Van Der Hoeven

Warren W Grunbok

William R Milani

De Tran

Henry Yeh

Cheryl Jean Herdey

Douglas R Moran

Steven Platt

Robert Henry Kruggel

Sundar Sankarasubramanian

Steven Harley Lamphier

Christopher Kanyuck

Eric Stephen Machat

An integrated circuit device includes functional circuitry including transistors, and testing circuitry configured to test effects of different layouts of the functional circuitry, relative to physical features of the integrated circuit device, on operation of the transistors. The testing circuitry includes at least one first test circuit having a first physical relationship relative to the physical features of the integrated circuit device, at least one second test circuit having a second physical relationship, different from the first physical relationship, relative to the physical features of the integrated circuit device, and sensing circuitry for reading outputs of the at least one first test circuit and the at least one second test circuit. Imbalance circuitry is configured to apply compensation to the functional circuitry to compensate for a sensed imbalance. There may be a plurality of instances of the first test circuit, and a plurality of instances of the second test circuit.

Built-in circuit for testing process and layout effects of an integrated circuit die

A semiconductor device includes circuitry configured for faster bitcell operation. That circuitry includes a plurality of bitcells readable as one of a '0' value and a ‘1’ value, and voltage generation circuitry configured to apply an activation voltage to activate selected bitcells in the plurality of bitcells for reading. The voltage generation circuitry is further configured to switch between an overdrive mode and a steady-state mode where the voltage generation circuitry applies a first voltage during the overdrive mode and the voltage generation circuitry applies a second voltage, less than the first voltage, during the steady-state mode, interconnect circuitry configured to couple the plurality of bitcells to reading circuitry. The reading circuitry is configured to receive a differential signal from a bitcell and amplify the differential signal to a full digital logic level. The full digital logic level corresponds to one of the ‘0’ value and the ‘1’ value.

Method and apparatus for faster bitcell operation

A semiconductor device includes circuitry configured to derive a physical unclonable function. The circuitry includes a plurality of bitcells, each bitcell being readable as one of a '0' value and a ‘1’ value, and sense amplifier circuitry configurable to read values from the plurality of bitcells. The sense amplifier circuitry includes margin circuitry configurable (i) to selectably bias reading of the plurality of bitcells toward one of ‘0’ values and ‘1’ values, (ii) to identify addresses of bitcells having a stable ‘1’ value when the margin circuitry is configured to bias reading of the plurality of bitcells toward ‘0’ values, and (iii) to identify addresses of bitcells having a stable ‘0’ value when the margin circuitry is configured to bias reading of the plurality of bitcells toward ‘1’ values. Each bitcell in the plurality of bitcells may include a differential transistor pair.

Structures and methods for deriving stable physical unclonable functions from semiconductor devices

A charge pump circuit includes a charge pump configured to increase a voltage of an input signal to generate a voltage-boosted input signal, output the voltage-boosted input signal in response to a determination that the voltage-boosted input signal is greater than or equal to a threshold, and connect the charge pump to a supply voltage to pre-charge the charge pump in response to a determination that the voltage-boosted input signal is less than the threshold. The charge pump circuit includes bandgap reference generator configured to receive the voltage-boosted input signal and output, based on the voltage-boosted input signal, a voltage reference signal to a device that operates in accordance with the supply voltage.

Charge pump circuit with internal pre-charge configuration

A voltage boost circuit for eDram using thin oxide field effect transistors (FETs) is disclosed. The voltage boost circuit includes a boost capacitor which is precharged with a precharge voltage in a precharge stage and which provides a boosted supply voltage to a thin oxide FET during a pump phase. The voltage boost circuit further include a drive capacitor which provides a turn on voltage to the thin oxide FET so that the boosted supply voltage can pass to an output node in the pump phase.

Voltage boost circuit

Methods produce IC devices that include a multiplexor that is electrically connected to a bandgap reference generator and a charge pump. The multiplexor receives voltage levels of a voltage-boosted clock signal being output by the charge pump to the bandgap reference generator. The multiplexor outputs, to the charge pump, either: a retry signal (if the voltage levels of the voltage-boosted clock signal being output by the charge pump are below a voltage threshold) or a pump signal (if the voltage levels of the voltage-boosted clock signal being output by the charge pump are not below the voltage threshold). The pump signal causes the charge pump to output the voltage-boosted clock signal to the bandgap reference generator. The retry signal causes the charge pump to not output the voltage-boosted clock signal to the bandgap reference generator, and instead to precharge the charge pump.

Charge pump circuit with built-in-retry

The present disclosure relates to customization of a circuit layout using information from a netlist, and more particularly, to customization of a circuit layout using embedded formulas and a netlist. The system includes a CPU, a computer readable memory, and a computer readable storage device. The system also includes first program instructions to generate a graphical layout of a circuit, second program instructions to place a text formula on the graphical layout of the circuit, and third program instructions to activate the text formula in order to customize the graphical layout of the circuit. The first program instructions, the second program instructions, and the third program instructions of the system are stored on the computer readable storage device for execution by the CPU via the computer readable memory.

Netlist editing of graphical data

Charge pump circuit includes a plurality of boost capacitors. An output charge of the charge pump circuit is adjusted by selecting a number of the boost capacitors at least one of using a digital control word and programming of a wiring level. A method of boosting supply voltage uses a charge pump circuit. The method includes adjusting an output charge of the charge pump circuit by selecting a number of boost capacitors at least one of using a digital control word and by programming of a wiring level.

Charge pump system and method utilizing adjustable output charge and compilation system and method for use by the charge pump

A method and structure is disclosed for serially storing and retrieving fuse information to and from a non-scannable static random access memory (SRAM) array within an embedded DRAM structure. The SRAM array is part of a scan chain and is connected to upstream and downstream latches that make up the scan chain. Various data is serially scanned into the scan chain. As the data flows through the entire scan chain, the invention counts the number of bits scanned into the embedded DRAM structure using a counter. The counter can be included within the embedded DRAM structure. After the counter counts to an amount equal to the number of bits of storage of all downstream scan latches in the scan chain, the invention loads the fuse information into a shift register. When the shift register is full, the invention loads the contents of the shift register to a SRAM line. The lengths of the shift register and the SRAM line are equal to a fuse word. The invention repeats these processes of loading the shift register and loading the SRAM array until the SRAM array is full. The fuse information is read from the SRAM array by simply specifying an address in the SRAM array.

Method and apparatus for implementing DRAM redundancy fuse latches using SRAM

A column redundancy system including a column redundancy apparatus for performing a redundancy swapping operation of column elements within the individual micro-cells. The column redundancy apparatus further includes a fuse information storage device, a first bank address decoding mechanism decodes a read bank address corresponding to a first micro-cell accessed for a read operation, and a second bank address decoding mechanism decodes a write bank address corresponding to a second micro-cell accessed for a write operation. If there is at least one defective column element contained within the first micro-cell, then the column redundancy apparatus generates an internal column address corresponding to the at least one defective column element in the first micro-cell. Likewise, if there is at least one defective column element contained within the second micro-cell, then the column redundancy apparatus generates an internal column address corresponding to the at least one defective column element in the second micro-cell.

Column redundancy system and method for a micro-cell embedded DRAM (e-DRAM) architecture

An on-chip I/O timings measurement circuit that improves measurement accuracy compared to conventional external test methods. This circuit guarantees AC timing specifications that are too small for the measurement capabilities of today's high-frequency memory testers. This system in incorporated into the SRAM via the JTAG interface and a JTAG private instruction. A private instruction refers to an unused instruction from the industry-standard public instruction set. Private instructions are usually reserved for the manufacturer, but may be provided to the user as an enhancement to the standard JTAG instruction set.

On-chip method for measuring access time and data-pin spread

Growing community of inventors

Colchester, VT, United States of America

Dale E Pontius