Texas Instruments Corporation

Dale E Hocevar

Alan Gatherer

Ching-Yu Hung

Carl E Lemonds, Jr

Anuj Batra

Manish Goel

Yuming Zhu

Yanni Chen

Armelle Laine

Raphael Defosseux

Yetung Paul Chiang

Encoder circuitry for applying a low-density parity check (LDPC) code to information words is disclosed. The encoder circuitry takes advantage of a macro matrix arrangement of the LDPC parity check matrix in which the parity portion of the parity check matrix is arranged as a macro matrix in which all block columns but one define a recursion path. The parity check matrix is factored so that the last block column of the parity portion includes an invertible cyclic matrix as its entry in a selected block row, with all other parity portion columns in that selected block row being zero-valued, thus permitting solution of the parity bits for that block column from the information portion of the parity check matrix and the information word to be encoded. Solution of the other parity bits can then be readily performed, from the original (non-factored) parity portion of the parity check matrix, following the recursion path.

Simplified LDPC encoding for digital communications

A method and systems for reducing the complexity of a parity checker are described herein. In at least some preferred embodiments, a parity-check decoder includes column store units and one or more alignment units, which are coupled to the column store units. The column store units outnumber the alignments units.

Parity check decoder architecture

A system for decoding in layers data received from a communication channel, comprising a first adder module adapted to determine an extrinsic estimate using a probability value estimate and a check node value estimate, the probability value estimate and the check node value estimate associated with a parity check matrix. The system also comprises a plurality of parity check update modules (PCUMs) in parallel with each other, coupled to the first adder module and adapted to update the check node value estimate, and a second adder module coupled to the plurality of PCUMs and adapted to update the probability value estimate using the extrinsic estimate and the updated check node value estimate. The PCUMs process at least some columns of at least some rows of the parity check matrix in a serial fashion.

Layered decoding of low density parity check (LDPC) codes

Transceiver circuitry for use in a multiple-input, multiple-output (MIMO), orthogonal frequency-division multiplexing (OFDM), communications environment, is disclosed. Error correction coding according to a fixed-block size code, such as low density parity check (LDPC) coding, is implemented. The codeword length, and codeword arrangement, are selected by determining a minimum number of OFDM symbol periods required for a payload size, and the number of available information bits in those symbol periods. A rule-based approach, for example in a table, is used to select the codeword length, and the number of codewords required. Shortening is then applied to the code, followed by determining whether puncturing or repeating of bits is necessary to efficiently use the available OFDM symbols.

Encoding for digital communications in a multiple-input, multiple-output environment

A low density parity check (LDPC) code for a belief propagation decoder circuit is disclosed. LDPC code is arranged as a macro matrix (H) representing block columns and block rows of a corresponding parity check matrix (H). Each non-zero entry corresponds to a permutation matrix with a shift corresponding to the position of the permutation matrix entry in the macro matrix. The block columns are grouped, so that only one column in the group contributes to the parity check sum in a row. A parity check value estimate memory is arranged in banks logically connected in various data widths and depths. A parallel adder generates extrinsic estimates for generating new parity check value estimates that are forwarded to bit update circuits for updating of probability values. Parallelism, time-sequencing of ultrawide parity check rows, and pairing of circuitry to handle ultrawide code rows, are also disclosed.

Hardware-efficient low density parity check code for digital communications

Transceiver circuitry for use in a multiple-input, multiple-output (MIMO), orthogonal frequency-division multiplexing (OFDM), communications environment, is disclosed. Error correction coding according to a fixed-block size code, such as low density parity check (LDPC) coding, is implemented. A specific LDPC code with excellent error rate performance is disclosed.

High-performance LDPC coding for digital communications in a multiple-input, multiple-output environment

A communications transceiver for transmitting and receiving coded communications, with the coding corresponding to a low-density parity check code, is disclosed. A set of available code word lengths and code rates are to be supported by the transceiver. These available code word lengths and code rates are implemented as a subset of starting code word lengths, which are length-reduced by shortening and puncturing selected bit positions in the starting code word length to attain the desired one of the available code word lengths and code rates. The bit positions to be shortened and punctured are selected in a manner that avoids interference between the shortened and punctured bit positions, and that attains excellent code performance.

Simplified decoding using structured and punctured LDPC codes

A method of decoding in layers data received in a communication system, comprising receiving a codeword containing a plurality of elements and translating the plurality of elements into probability values by dividing the rows of at least one column of a parity check matrix associated with the codeword into groups and processing at least some of the groups separately.

Layered decoding approach for low density parity check (LDPC) codes

A low density parity check (LDPC) code that is particularly well adapted for hardware implementation of a belief propagation decoder circuit is disclose& The LDPC code is arranged as a macro matrix (H) whose rows and columns represent block columns and block rows of a corresponding parity check matrix (H). Each non-zero entry corresponds to a permutation matrix, such as a cyclically shifted identity matrix, with the shift corresponding to the position of the permutation matrix entry in the macro matrix. The block columns of the macro matrix are grouped, so that only one column in the macro matrix group contributes to the parity check sum in any given row. The decoder circuitry includes a parity check value estimate memory which may be arranged in banks that can be logically connected in various data widths and depths. A parallel adder generates extrinsic estimates that are applied to parity check update circuitry for generating new parity check value estimates. These parity check value estimates are stored back into the memory, and are forwarded to bit update circuits for updating of probability values for the input nodes. Variations including parallelism, time-sequencing of ultrawide parity check rows, and pairing of circuitry to handle ultrawide code rows, are also disclosed.

Encoder circuitry for applying a low-density parity check (LDPC) code to information words is disclosed. The encoder circuitry takes advantage of a macro matrix arrangement of the LDPC parity check matrix in which a left-hand portion of the parity check matrix is arranged as an identity macro matrix, each entry of the macro matrix corresponding to a permutation matrix having zero or more circularly shifted diagonals. The encoder circuitry includes a cyclic multiply unit, which includes a circular shift unit for shifting a portion of the information word according to shift values stored in a shift value memory for the matrix entry, and a bitwise exclusive-OR function for combining the shifted entry with accumulated previous values for that matrix entry. Circuitry for solving parity bits for row rank deficient portions of the parity check matrix is also included in the encoder circuitry.

Efficient encoder for low-density-parity-check codes

A low density parity check (LDPC) code that is particularly well adapted for hardware implementation of a belief propagation decoder circuit () is disclosed. The LDPC code is arranged as a parity check matrix (H) whose rows and columns represent check sums and input nodes, respectively. The parity check matrix is grouped into subsets of check sum rows, in which the column weight is a maximum of one. The decoder circuitry includes a parity check value estimate memory (). Adders () generate extrinsic estimates, from immediately updated input node probability estimates, and the extrinsic estimates are applied to parity check update circuitry () for generating new parity check sum value estimates. These parity check sum value estimates are stored back into the memory (), and after addition with the extrinsic estimates, are stored in a column sum memory () of a corresponding bit update circuit () as updated probability values for the input nodes.

Layered low density parity check decoding for digital communications

By utilizing an additional counter and monitoring the maximum state metric at each stage, only forward progressing modulo wrap-arounds will occur and these can be counted. After decoding this count information, it can be used with the initial and final state metric values from the decoder to compute the desired full path metric. The method only requires monitoring state metric wrap-arounds moving in one direction and hence only needs to increment the extra counter as opposed to having to do likewise in the opposite direction. In another embodiment, the method can handle both forward and backward progressions by incrementing and decrementing a counter.

Computing the full path metric in viterbi decoding

A Viterbi decoder system is provided in accordance with the present invention. The decoder system includes a State Metric Update unit including a state metric memory and a cascaded Add/Compare/Select (ACS) unit. The cascaded ACS unit comprises a plurality of serially coupled ACS stages for performing a plurality of ACS operations in conjunction with the state metric memory. An ACS stage is operable to identify a plurality of path decisions and path differences and communicate the identified path decisions and the identified path differences to a next ACS stage coupled thereto. The decoder also includes a Traceback unit for storing a set of accumulated path decisions in a traceback memory associated therewith, and performing a traceback on the set of accumulated path decisions. The path decisions associated with the ACS stage and the next ACS stage are accumulated as a set during the ACS operations before being written to the traceback memory, thereby minimizing accesses to the traceback memory. The path differences associated with the ACS stage and the next ACS stage provide a reliability estimation of the correctness of the path decisions.

Enhanced viterbi decoder for wireless applications

A Viterbi decoder system is provided in accordance with the present invention. The decoder system includes a State Metric Update unit including a state metric memory and a cascaded Add/Compare/Select (ACS) unit. The cascaded ACS unit comprises a plurality of serially coupled ACS stages for performing a plurality of ACS operations in conjunction with the state metric memory. An ACS stage is operable to identify a plurality of path decisions and communicate the identified path decisions to a next ACS stage coupled thereto. A Traceback unit is provided for storing a set of accumulated path decisions in a traceback memory associated therewith, and performing a traceback on the set of accumulated path decisions. The path decisions associated with the ACS stage and the next ACS stage are accumulated as a set during the ACS operations before being written to the traceback memory, thereby minimizing accesses to the traceback memory.

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Plano, TX, United States of America

Dale E Hocevar