Advanced Micro Devices Corporation

Sony Corporation

Other

Globalfoundries Inc.

Legerity, Inc.

Advanced Micro Systems, Inc.

Dale E Gulick

Larry David Hewitt

Geoffrey S Strongin

Brian C Barnes

Andy Lambrecht

Mike Webb

James B Keller

William Alexander Hughes

Munehiro Yoshikawa

Siegfried Kay Hesse

Frederick Daniel Weber

Derrick R Meyer

David N Suggs

Geoffrey S S Strongin

Terry G Lawell

Joseph W Peterson

Alan F Hendrickson

Scott E Swanstrom

Frank P Helms

Paul C Miranda

Glen W Brown

David E Norris

Michael E Spak

James E Bowles

Hiroshi Matsubara

Martin P Soques

Michael Hogan

Charles Crowe

Scott A White

David S Christie

Kevin John McGrath

Terry Lynn Cole

Satoru Maeda

Paul G Schnizlein

Alfredo R Linz

Joe W Peterson

Carlin D Cabler

Geoffrey E Brehmer

Frank Barth

James O Mergard

Shin Saito

Alan R Hendrickson

Jeffrey M Blumenthal

Kazushige Tsurumi

Ryan E Feemster

Joerg Winkler

Timothy C Maleck

David J Guercio

Manabu Oonishi

Dean Grumlose

Alan T Torok

Mark Douglas Hummel

Gerald Robert Talbot

John G Bartkowiak

Drew Jon Dutton

Brian D McMinn

Michael T Wisor

Alfred C Hartmann

R Stephen Polzin

Shwetal Arvind Patel

Richard W Reeves

Merle L Miller

Ross Voigt La Fetra

Gabriele Sartori

Herbert M Chen

Masaru Nonogaki

Jonathan P Dowling

Toshiaki Iimura

Mark Luedtke

Toshihiro Fujita

James R Foppiano

David G Selig

A cable solution which enables a flash controller which is located on a motherboard of an information processing system to be coupled with a memory socket which is located within a passive socket panel. In certain embodiments, a cable and header arrangement is provided for connecting the motherboard to the chassis socket panel card. This arrangement allows the front panel card to be simplified (i.e., to be a passive card). In certain embodiments, the solution uses a cable structure such as that used for integrated drive electronics (IDE) type disk drive cables or an ultra AT attachment (U-ATA) type cable. The cable solution provides a low cost solution which offers multiple performance options for a single cost. For example, the cable solution functions with both a standard memory card socket as well as a high speed memory card. Also, in certain embodiments, the header connections include ground signal paths interposed among the data signal paths. The board header connectors are the same for both the standard and high speed socket configurations, only the cable changes between the standard and high speed configurations.

Non-volatile memory controller cable arrangement

A method and apparatus is provided for processing tasks with failure recovery. The method includes storing one or more tasks in a queue, wherein each task has an associated exit routine, and determining at least one task to process based on a priority scheme. The method further includes processing the at least one task, and calling the exit routine based on determining that the task has not completed processing within a preselected period of time.

Processing tasks with failure recovery

A computer system includes a processor which may initialize a secure execution mode by executing a security initialization instruction. Further, the processor may operate in the secure execution mode by executing a secure operating system code segment. The computer system also includes an input/output (I/O) interface coupled to the processor via an I/O link. The I/O interface may receive transactions performed as a result of the execution of the security initialization instruction. The transactions include at least a portion of the secure operating system code segment. The I/O interface may also determine whether the processor is a source of the transactions. The computer system further includes a security services processor coupled to the I/O interface via a peripheral bus. The I/O interface may convey the transactions to the security services processor dependent upon determining that the processor is the source of the transactions.

Computer system including a secure execution mode-capable CPU and a security services processor connected via a secure communication path

The initialization of a computer system including a secure execution mode-capable processor includes storing a secure operating system code segment loader to a plurality of locations corresponding to a particular range of addresses within a system memory. The method also includes executing a security initialization instruction. Executing the security initialization instruction may cause several operations to be performed including transmitting a start transaction including a base address of the particular range of addresses. In addition, executing the security instruction may also cause another operation to be performed including retrieving the secure operating system code segment loader from the system memory and transmitting the secure operating system code segment loader for validation as a plurality of data transactions.

Initialization of a computer system including a secure execution mode-capable processor

A system including a host coupled to a serially connected chain of memory modules. In one embodiment, each of the memory modules includes a memory control hub for controlling access to a plurality of memory chips on the memory module. The memory modules are coupled serially in a chain to the host via a plurality of memory links. Each memory link may include an uplink for conveying transactions toward the host and a downlink for conveying transactions originating at the host to a next memory module in the chain. The uplink and the downlink may convey transactions using packets that include control and configuration packets and memory access packets. The memory control hub may convey a transaction received on a first downlink of a first memory link on a second downlink of a second memory link independent of decoding the transaction.

System including a host connected to a plurality of memory modules via a serial memory interconnect

A computer system including a bus bridge for bridging transactions between a secure execution mode-capable processor and a security services processor. The bus bridge may include a transaction source detector, a configuration header and control logic. The transaction source detector may receive a security initialization transaction performed as a result of execution of a security initialization instruction. Further, the transaction source detector may determine whether the secure execution mode-capable processor is a source of the security initialization transaction. The configuration header may provide storage of information associated with the security services processor. The control logic may determine whether the security services processor is coupled to the bus bridge via a non-enumerable, peripheral bus. The control logic may also cause the configuration header to be accessible during a boot-up sequence in response to determining that the security services processor is coupled to the non-enumerable, peripheral bus.

Computer system including a bus bridge for connection to a security services processor

Computer system configuration resources include first and second control circuits in respective first and second integrated circuits. A communication link, which transfers data over a plurality of logical pipes, connects the two integrated circuits. Configuration of the link utilizes a link bridge that includes upstream (located closest to the CPU) configuration registers that are within the first control circuit and downstream ((located farthest from the CPU) configuration registers within the second control circuit. A link header, which includes upstream data for the first control circuit and down stream data for the second control circuit, is used to initialize the link. The upstream and downstream data may include information specifying the size of the communication link.

Configuring a communication link interface

A computer system may include multiple processing nodes, one or more of which may be coupled to separate memories which may form a distributed memory system. The processing nodes may include caches, and the computer system may maintain coherency between the caches and the distributed memory system. Particularly, the computer system may implement a flexible probe command/response routing scheme. The scheme may employ an indication within the probe command which identifies a receiving node to receive the probe responses. For example, probe commands indicating that the target or the source of transaction should receive probe responses corresponding to the transaction may be included. Probe commands may specify the source of the transaction as the receiving node for read transactions (such that dirty data is delivered to the source node from the node storing the dirty data). On the other hand, for write transactions (in which data is being updated in memory at the target node of the transaction), the probe commands may specify the target of the transaction as the receiving node. In this manner, the target may determine when to commit the write data to memory and may receive any dirty data to be merged with the write data.

Flexible probe/probe response routing for maintaining coherency

An integrated circuit, a computer system, and a method for authorizing RMCP requests. The method includes receiving a request for a system action and initiating a timer. The method also includes generating an authorization request for the system action and evaluating a result of the authorization request for the system action if received before an expiration of the timer. The method also includes granting the request for the system action if the expiration of the timer occurs before the result of the authorization request for the system action is received.

Remote management mechanism to prevent illegal system commands

A method and system for enhanced security and manageability using secure storage. The system may include a crypto-processor and a memory coupled to receive memory transactions through the crypto-processor. The memory transactions are passed to the memory by the crypto-processor. The system may include a first processor, a second processor coupled to the first processor, and a storage device operably coupled to the first processor through the second processor. The second processor is configured to control access to the storage device. The method includes transmitting a request for a memory transaction for a storage location in the storage device and receiving the request for the memory transaction at the crypto-processor. The method also includes determining if the memory transaction is authorized for the storage location, and passing the request for the memory transaction to the storage device if the memory transaction is authorized for the storage location.

Enhanced security and manageability using secure storage in a personal computer system

A computer system includes a processor which may initialize a secure execution mode by executing a security initialization instruction. Further, the processor may operate in the secure execution mode by executing a secure operating system code segment. The computer system also includes a system memory configured to store data in a plurality of locations. The computer system also includes a memory controller which may selectively clear the data from a programmed range of the memory locations of the system memory when enabled in response to a reset of the processor.

Computer system employing a trusted execution environment including a memory controller configured to clear memory

An integrated circuit, a client computer system, and a method for operating the integrated circuit in the client computer system. The integrated circuit includes a first bus interface logic for coupling to a first external bus, a microcontroller configured as an Alert Standard Format management engine, and a watchdog timer coupled to the microcontroller. The microcontroller is further configured to receive Alert Standard Format sensor data over the first external bus. The watchdog timer is coupled to receive a reset input upon a predetermined change in a system state. The watchdog timer is further configured to provide an indication to the microcontroller in response to an expiration of the watchdog timer.

ASF state determination using chipset-resident watchdog timer

A host controller such as a USB host controller in a southbridge, and a corresponding operation method are provided. The host controller comprises a descriptor fetch unit that is adapted to send out requests for descriptors and receive descriptors in reply to the requests. The descriptors are data structures for describing attributes of the data transfer to and from the devices controlled by the host controller. The host controller further comprises a descriptor cache that is adapted to store prefetched descriptors. The descriptor cache is further adapted to store individual replacement control values for at least a part of the stored prefetched descriptors. The host controller is arranged to replace a stored prefetched descriptor in the descriptor cache by a newly prefetched descriptor based on the replacement control value that is associated with the stored prefetched descriptor. The replacement technique may improve the overall efficiency of the host controller operation.

Controlling the replacement of prefetched descriptors in a cache

A message based power management approach is utilized to provide power management for a multi-processor system. A power management message is received at one processor of the multi-processor system over an input/output communication link that provides input/output access for the processors of the multi-processor system. The power management message includes a power management field encoding a power management state for processors of the multi-processor system. The processor that received the power management message over the input/output communication link sends a power management message to other processors in the multi-processor system over one or more inter-processor communication links encoding the power management state.

Message based power management in a multi-processor system

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Austin, TX, United States of America

Dale E Gulick