Micron Technology Incorporated

Intel Corporation

Other

Sony Semiconductor Solutions Corporation

Dale Collins

Rita J Klein

Swapnil Lengade

Andrea Gotti

Richard H Lane

Durai Vishak Nirmal Ramaswamy

Warren M Farnworth

Scott E Sills

Christopher W Petz

Steven M McDonald

Yongjun Jeff Hu

David A Kewley

Shuichiro Yasuda

David S Pratt

Beth R Cook

Radhakrishna Kotti

Raju Ahmed

Trupti D Gawai

Ahmed M Elsied

Chelsea M Jordan

Joe Lindgren

Nishant Sinha

F Daniel Gealy

Allen McTeer

Karthik Sarpatwari

Lorenzo Fratin

Paul A Morgan

Stephen W Russell

Anna Maria Conti

Enrico Varesi

Matthew N Rocklein

Joseph Neil Greeley

Tuman Earl Allen, Iii

Lei Bi

Marko Milojevic

Daniel Gealy

Pavan Reddy K Aella

Si-Young Park

Fred Daniel Gealy, Iii

Fabio Pellizzer

James E Green

Noel Rocklein

Paolo Fantini

Pengyuan Zheng

Mark S Korber

Srividya Krishnamurthy

Tsz-Wah Chan

Methods of manufacturing semiconductor devices, and associated systems and devices, are disclosed herein. In some embodiments, a method of manufacturing a semiconductor device includes forming an opening in an electrically insulative material at least partially over a first electrically conductive feature and a second electrically conductive feature. The method can further include forming a ring of electrically conductive material around a sidewall of the insulative material defining the opening, wherein the ring of electrically conductive material includes (a) a first via portion over the first electrically conductive feature, (b) a second via portion over the second electrically conductive feature, and (c) connecting portions extending between the first and second via portions. Finally, the method can include removing the connecting portions of the ring of electrically conductive material to electrically isolate the first via portion from the second via portion.

Methods for forming conductive vias, and associated devices and systems

Methods, systems, and devices for chalcogenide memory device compositions are described. A memory cell may use a chalcogenide material having a composition as described herein as a storage materials, a selector materials, or as a self-selecting storage material. A chalcogenide material as described herein may include a sulfurous component, which may be completely sulfur (S) or may be a combination of sulfur and one or more other elements, such as selenium (Se). In addition to the sulfurous component, the chalcogenide material may further include one or more other elements, such as germanium (Ge), at least one Group-III element, or arsenic (As).

Chalcogenide memory device compositions

Methods, systems, and devices for composite electrode material chemistry are described. A memory device may include an access line, a storage element comprising chalcogenide, and an electrode coupled with the memory element and the access line. The electrode may be made of a composition of a first material doped with a second material. The second material may include a tantalum-carbon compound. In some cases, the second may be operable to be chemically inert with the storage element. The second material may include a thermally stable electrical resistivity and a lower resistance to signals communicated between the access line and the storage element across a range of operating temperatures of the storage element as compared with a resistance of the first material.

Composite electrode material chemistry

Methods, systems, and devices for a resistive interface material are described. A memory device may be fabricated using a sequence of steps that include forming a stack of materials by depositing a first metal layer, depositing a first electrode layer on the metal layer, depositing a memory material on the first electrode layer to form one or more memory cells, depositing a second electrode layer on the memory material, and depositing a second metal layer on the second electrode layer. A lamina (or multiple) having a relatively high resistivity may be included in the stack of materials to reduce or eliminate a current spike that may otherwise occur across the memory cells during an access operation.

Resistive interface material

Methods, systems, and devices for techniques for forming memory structures are described. Forming a memory structure may include etching a stack of material including a conductive line, a first electrode and a sacrificial material to divide the stack of material into multiple sections. The process may further include depositing an oxide material in each of the first quantity of channels to form multiple oxide materials. The sacrificial material may be etched to form a second channel between two oxide materials of the multiple oxide materials. Memory material may be deposited over the two oxide materials and the second channel, which may create a void in the second channel between the memory material and the first electrode. The memory material may be heated to fill the void in the second channel.

Techniques for forming memory structures

A memory structure can include a memory cell and a first barrier layer having a maximum hydrogen diffusion coefficient of 1&#xd7;10cm/s, said first barrier layer adjacent to the memory cell to minimize contaminant movement to or from the memory cell.

Memory structures having improved write endurance

Devices and systems having a diffusion barrier for limiting diffusion of a phase change material including an electrode, a phase change material electrically coupled to the electrode, and a carbon and TiN (C:TiN) diffusion barrier disposed between the electrode and the phase change material to limit diffusion of the phase change material are disclosed and described.

Laminate diffusion barriers and related devices and methods

A semiconductor structure includes a plurality of stack structures overlying a substrate. Each stack structure includes a first chalcogenide material over a conductive material overlying the substrate, an electrode over the first chalcogenide material, a second chalcogenide material over the electrode, a liner on sidewalls of at least one of the first chalcogenide material or the second chalcogenide material, and a dielectric material over and in contact with sidewalls of the electrode and in contact with the liner. Related semiconductor devices and systems, methods of forming the semiconductor structure, semiconductor device, and systems, and methods of forming the liner in situ are disclosed.

Semiconductor devices including liners, and related systems

Some embodiments include methods for depositing copper-containing material utilizing physical vapor deposition of the copper-containing material while keeping a temperature of the deposited copper-containing material at greater than 100&#xb0; C. Some embodiments include methods in which openings are lined with a metal-containing composition, copper-containing material is physical vapor deposited over the metal-containing composition while a temperature of the copper-containing material is no greater than about 0&#xb0; C., and the copper-containing material is then annealed while the copper-containing material is at a temperature in a range of from about 180&#xb0; C. to about 250&#xb0; C. Some embodiments include methods in which openings are lined with a composition containing metal and nitrogen, and the lined openings are at least partially filled with copper-containing material. Some embodiments include semiconductor constructions having a metal nitride liner along sidewall peripheries of an opening, and having copper-containing material within the opening and directly against the metal nitride liner.

Semiconductor constructions; and methods for providing electrically conductive material within openings

A method of manufacture of a non-volatile memory system comprising: forming a dielectric layer having a hole; depositing a first electrode in the hole of the dielectric layer; applying an ion source layer over the first electrode; and depositing a second electrode over the ion source layer including: depositing an interface layer on the ion source layer, and applying a cap layer on the interface layer.

Non-volatile memory system with reliability enhancement mechanism and method of manufacture thereof

Doping a storage element, a selector element, or both, of a memory cell with a dopant including one or more of aluminum (Al), zirconium (Zr), hafnium (Hf), and silicon (Si), can minimize volume or density changes in a phase change memory as well as minimize electromigration, in accordance with embodiments. In one embodiment, a memory cell includes a first electrode and a second electrode, and a storage element comprising a layer of doped phase change material between the first and second electrodes, wherein the doped phase change material includes one or more of aluminum, zirconium, hafnium, and silicon. The storage element, a selector element, or both can be doped using techniques such as cosputtering or deposition of alternating layers of a dopant layer and a storage (or selector) material.

Doping of selector and storage materials of a memory cell

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Boise, ID, United States of America

Dale Collins