International Business Machines Corporation

Dale Arthur Heuer

Phillip C Schloss

Larry Lloyd Schroeder

Philip T Wu

Michael E Brossard

Ronald Lyle DeRemer

Michael J Sheehan

John F Roemer

Charles W McCallister

The disclosure shows a read only storage (ROS) formed of a matrix of rows and columns of field effect transistor (FET) devices which is personalized by the presence or absence of a gate at the memory device location. All circuits on the chip are controlled and restored to initial conditions by a single train of clock pulses including the row and column addresses, the array select and the output sensing. In addition the output signal is communicated directly to the output line control device without withdrawing current to set the outputs latch thereby making the output truely delayless.

Read only memory circuit

A single chip large scale integration processor processes its own on-chip control storage array while including the ability to also address supplemental off-chip control storage and to use such off-chip supplemental storage in substitution for portions of the on-chip storage. The processor further includes simplified arithmetic and logic (ALU) circuitry wherein the adder circuit has portions selectively gated to perform other functions with a reduced logic circuit requirement. Processor function is also enhanced by providing a read only storage (ROS) array in association with the ALU to provide multiple register loading and control functions in response to certain addresses. The processor also includes memory control circuitry that permits a group of like processors to access a single, external memory on a dynamic, prioritized basis.

Microprocessor system

A microprocessor has a common data bus coupled to a storage data register, two separate storage address registers and a storage control unit. The data register transfers data to and from a storage unit addressed by that address register selected by a gating means. The address registers can be independently incremented and decremented, and perform either a read or a write operation. All these functions are specified by signals produced from a control word held in the storage control unit.

Independently controllable multiple address registers for a data

A single chip large scale integration processor possesses its own on-chip control storage array while including the ability to also address supplemental off-chip control storage and to use such off-chip supplemental storage in substitution for portions of the on-chip storage. The processor further includes simplified arithmetic and logic (ALU) circuitry wherein the adder circuit has portions selectively gated to perform other functions with a reduced logic circuit requirement. Processor function is also enhanced by providing a read only storage (ROS) array in association with the ALU to provide multiple register loading and control functions in response to certain addresses. The processor also includes memory control circuitry that permits a group of like processors to access a single, external memory on a dynamic, prioritized basis.

An FET read only memory array having bit locations arranged in rows and columns utilizes a dynamic array and static sensing. A dynamic first address selects the gate line of a selected column and a second address selects the source line or lines to select one or more bits within the selected column. The presence or absence of a gate at a selected bit location determines whether a first or second logic level is present at the sense or drain line serving the bit location. An additional column of FET bit positions each with a gate has the gate line activated toward the conclusion of the cycle to provide a path to ground for the elimination of any charge on a sense line in preparation for the next succeeding cycle. The sensed output from a selected bit location is latched until reset.

Read only memory

A read only memory is organized as a matrix of field effect transistors wherein logic levels are determined by the presence or absence of a gate which permits transistor action. The memory is addressed using a gate decode tree which selects the gates of a column of matrix devices and a source decode tree which selects the source lines of a row of matrix devices. Sensing of the logic level at a selected location is accomplished by a change of state output sense circuit which dynamically senses and provides a static output using a polarity hold circuit. Clamped, boot-strapped inverter circuits are provided in both input and output circuitry to maintain voltage, at selected internal nodes at a voltage intermediate predetermined minimum and maximum values.

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Stewartville, MN, United States of America

Dale Arthur Heuer