Hayes Microcomputer Products, Inc.

National Data Corporation

Dale A Heatherington

Dennis E Puckett

Eugene C Jones

A quadrature differential phase shift keyed signal demodulator for use in a modem is shown. A delay circuit (12) delays an input signal for a portion of a baud time. Synchronous detectors (21, 23) mix the original and delayed input signals with coherent reference signals to obtain detected outputs which are alternately provided to a processor (60) by a multiplexer (25). The processor (60) determines the phase shift and provides the demodulated data. An offset baud clock phase locked loop (40) provides a baud clock which is offset by a ninety degree phase lag. The offset baud clock causes the multiplexer (25) to provide detected outputs to the processor (60) for the center one-half of each baud. The result is a demodulator with fewer components and an improved data error rate.

Band clock offset phase locked loop

An improved quadrature differential phase shift keyed signal demodulator for use in a modem is shown. A delay circuit (12) delays an input signal for a portion of a baud time. Synchronous detectors (21, 23) mix the original and delayed input signals with coherent reference signals to obtain detected outputs which are alternately provided to a processor (60) by a multiplexer (25). The processor (60) determines the phase shift and provides the demodulated data. An offset baud clock phase locked loop (40) provides a baud clock which is offset by a ninety degree phase lag. The offset baud clock caused the multiplexer (25) to provide detected outputs to the processor (60) for the center one-half of each baud. The result is a demodulator with fewer components and an improved data error rate.

Multiplexed PSK demodulator

A frequency synthesizer which has a constant resolution over an octave frequency range is disclosed. The frequency synthesizer has a presettable high speed counter, a low speed counter, an adjusting counter, and a count selector. The low speed counter provides a first output signal whose frequency is rapidly alternated between two closely-spaced frequencies so that the average frequency of the output signal is the desired frequency. The adjusting counter determines the period of time that each of the closely-spaced frequencies is present at the output. The count selector determines the frequency of each of the two closely-spaced frequencies. The frequency synthesizer also has a phase splitter and provides a second output signal which is also of the desired frequency but which is phase-shifted by ninety degrees from the first output signal.

Constant resolution frequency synthesizer

An FSK modem for coupling a standard data port (50) to a telephone line (45) in which the signal path between the phone line and the data port passes through a processor (55). When the modem is in a transparent mode of operation, for transmitting data, a timer (190) detects the passage of a predetermined period of time after the most recent data input signal input to a data port (50). If the next sequence of data signals corresponds to an escape character, the program (112) controlling the modem waits to see if a second occurrence of the predetermined period of time follows provision of the escape character. If this occurs, the modem switches to a command mode of operation in which it ceases to modulate and transmit signals and waits for commands to be entered at the data port. The same frequency detection apparatus (83, 192, 180) is used to both demodulate FSK encoded signals and detect the presence of a telephone ringing signal on the line. A pair of impedances (161, 162) provide alternate paths either through an input filtering network (167) or bypassing the network (135, 69) in a manner which allows the ring signals to pass directly to the input (69) of the frequency detector while assuring that only filtered FSK signals reach the input. Also shown is the use of the same frequency synthesizing apparatus (86, 253, 259) for generating FSK output signals and high group DTMF signals with appropriate switchable attenuation (88) provided in this signal path.

Modem with improved escape sequence mechanism to prevent escape in

An improved four-phase differential phase shift keyed modulator for use in a modem is shown. A microprocessor (15) generates two vectors of equal frequency and equal magnitude, but different relative phases, by reference to a cyclic sine table contained in a read only memory (22). Values of the two vectors are summed and provided as an output (32) to a digital to analog converter (35). The phase shift of the carrier in a phase plane with reference to a predetermined reference phase (86) shows that the path taken by a vector in the phase plane defines a straight line (88) between two phase values by which dibits are encoded. The result is lower out-of-band transmitted signals resulting in a relatively simple transmit filter (37).

Digital PSK modulator for modem

An FSK modem for coupling a standard data port (50) to a telephone line (45) in which the signal path between the phone line and the data port passes through a processor (55). The same frequency detection apparatus (83, 192, 180) is used to both demodulate FSK encoded signals and detect the presence of a telephone ringing signal on the line. A pair of impedances (161, 162) provide alternate paths either through an input filtering network (167) or bypassing the network (135, 69) in a manner which allows the ring signals to pass directly to the input (69) of the frequency detector while assuring that only filtered FSK signals reach the input. Also shown is the use of the same frequency synthesizing apparatus (86, 253, 259) for generating FSK output signals and high group DTMF signals with appropriate switchable attenuation (88) provided in this signal path.

Modem with low part count and improved demodulator

A read only memory apparatus for use in a byte oriented processor (10) includes a data selector (25) which responds to the first memory fetch of a memory reference instruction (40, 28) to provide a selected set of output bits (20) from a read only memory to a particular portion (22) of the processor data bus. The apparatus provides a set of replacement bits (26) to the same portion of the data bus (22) in response to each occurrence of detection (29, 30') of the most significant byte of a such memory reference instruction being provided to the data bus. The replacement bits occur in the most significant byte of the address referred to in the memory reference instruction and prevents the processor's program counter from jumping out of the address space alloted to the read only memory. In the preferred form, the same set of switches (17) used with an address decoder (15) to define the location of the ROM circuit in the address space of the processor's memory also provides replacement bits.

Relocatable read only memory

A device that permits local or remote access to data circuits for the purpose of monitoring, testing and performing diagnostics. It may be used to issue commands to perform various functions whereby the device couples a given circuit to a telephone line in response to coded signals identifying the device and the circuit to be interrogated.

Growing community of inventors

Decatur, GA, United States of America

Dale A Heatherington