Samsung Electronics Co., Ltd.

Dal-Hee Lee

Jae-Woo Seo

Ha-Young Kim

Tae-Joong Song

Sung-We Cho

Sung-Wee Cho

Sang-Hoon Baek

Jin-Young Lim

Jae-Ha Lee

Jong-Hoon Jung

Gi-young Yang

Min-Ho Park

Chang-beom Kim

Hyun-jeong Roh

Jung-Ho Do

Jin-Tae Kim

Hee-Sung Kang

Jae-Ho Park

Suk-Joo Lee

Joong-won Jeon

Jung-ho Do

Hyeon-gyu You

Dae-Ho Yoon

An integrated circuit may include a first active region and a second active region, and the first and second active regions may extend on a substrate in a first horizontal direction in parallel to each other and have different conductivity types from each other. A first gate line may extend in a second horizontal direction crossing the first horizontal direction, and may form a first transistor with the first active region. The first transistor may include a gate to which a first input signal is applied. The first gate line may include a first partial gate line that overlaps the first active region in a perpendicular direction and that has an end on a region between the first and second active regions.

Integrated circuits having cross-couple constructs and semiconductor devices including integrated circuits

A scan flip-flop includes an input unit and a flip-flop. The input unit is configured to select one signal from among a data input signal and a scan input signal to supply the selected one signal as an internal signal according to an operation mode. The flip-flop is configured to latch the internal signal according to a clock signal. The flip-flop includes a cross coupled structure that includes first and second tri-state inverters which share a first output node and face each other.

Scan flip-flop and scan test circuit including the same

An integrated circuit includes a first conductive pattern in a first conductive layer, a second conductive pattern in a second conductive layer over the first conductive layer, and a via electrically connected with the first conductive pattern and the second conductive pattern to allow a first current flowing from the first conductive pattern to the second conductive pattern and a second current flowing from the second conductive pattern to the first conductive pattern to pass through at different times. The via is placed on the first conductive pattern so that a path of the first current does not overlap with a path of the second current in the first conductive pattern.

Integrated circuit including interconnection and method of fabricating the same, the interconnection including a pattern shaped for mitigating electromigration

Provided is an integrated circuit including: at least one active region extending in a first row in a first direction; at least one active region extending in a second row in the first direction; and a multiple height cell including the at least one active region in the first row, the at least one active region in the second row, at least one gate line extending in a second direction crossing the first direction, wherein each of the at least one active region in the first row and the at least one active region in the second row is terminated by a diffusion break.

Integrated circuit including multiple-height cell and method of manufacturing the integrated circuit

Integrated circuit including interconnection and method of fabricating the same, the interconnection including a pattern shaped and/or a via disposed for mitigating electromigration

An engineering change order (ECO) base cell and an integrated circuit (IC) including the ECO base cell are provided. The IC includes a plurality of standard cells and at least one engineering change order (ECO) base cell. The ECO base cell has a layout that is generated based on a layout of a functional cell corresponding to a first circuit including a plurality of logic gates.

Engineering change order (ECO) cell, layout thereof and integrated circuit including the ECO cell

Methods of generating an integrated circuit layout include forming a standard cell by providing a first active area adjacent to a first cell boundary line. The first active area is spaced apart from the first cell boundary line by a first distance. A second active area is provided adjacent to a second cell boundary line. The second cell boundary line opposes the first cell boundary line. The second active area is spaced apart from the second cell boundary line by a second distance. Fins are formed on the first and second active areas. The fins extend in a first direction and parallel to one another in a second direction substantially perpendicular to the first direction. The first cell boundary line is parallel to the fins. The first distance and the second distance remain constant when a number of the fins on the first and second active areas is changed.

Methods of generating integrated circuit layout using standard cell library

An integrated circuit (IC) includes at least one unit cell. The at least one unit cell includes a first bit circuit configured to process a first bit signal, a second bit circuit configured to process a second bit signal, a first well spaced apart from boundaries of the at least one unit cell and biased to a first voltage, and a second well biased to a second voltage that is different from the first voltage. Each of the first and second bit circuits includes at least one transistor from among a plurality of transistors disposed in the first well.

Integrated circuit and semiconductor device including the same

An integrated circuit (IC) includes a first circuit, a first well and a second circuit. The first circuit is disposed on a substrate and configured to shift a first bit signal between a first voltage logic level and a second logic voltage level. The first well is disposed in a cell on the substrate and biased to a first voltage. The first well is spaced apart from a first edge of the cell. The second well is disposed in the cell and biased to a second voltage. The second well is disposed to contact a second edge of the cell opposite to the first edge. The first circuit includes a plurality of transistors respectively disposed in the first and second wells.

A scan flip-flop includes an input unit and a flip-flop. The input unit is configured to select one signal from among a data input signal and a scan input signal to supply the selected one signal as an internal signal according to an operation mode. The flip-flop os configured to latch the internal signal according to a clock signal. The flip-flop includes a cross coupled structure that includes first and second tri-state inverters which share a first output node and face each other.

A method of designing an integrated circuit includes a processor receiving input data initially-defining the integrated circuit using a plurality of first standard cells designed to optimize a performance or yield characteristic. The processor substitutes at least one second standard cell designed to optimize a different performance or yield characteristic from that for which the first standard cells were optimized for a corresponding one of the first standard cells. The processor generates output data defining the integrated circuit including the second standard cell. The substituted second standard cell has the same function as the corresponding first standard cell for which it was substituted.

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Seoul, South Korea

Dal-Hee Lee